Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.3. Host Connection to OpenCL Kernels

The PCIe® host needs to pass commands and arguments to the OpenCL™ kernels via the control register access (CRA) Avalon® agent port that each OpenCL kernel generates.

The OpenCL Kernel Interface for S10 (kernel_interface) component exports an Avalon® host interface (kernel_cra) that connects to this agent port. The OpenCL Kernel Interface for S10 component also generates the kernel reset (kernel_reset) that resets all logic in the kernel clock domain. The kernel_interface component also bridges the interrupt signal generated by the kernel to the pcie_irq block.

The Intel® Stratix® 10 FPGA Development Kit Reference Platform has one DDR4 memory bank. As a result, the Reference Platform instantiates the OpenCL Kernel Interface component and sets the Number of global memory systems parameter to 1.

Did you find the information on this page useful?

Characters remaining:

Feedback Message