Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Public
Document Table of Contents

2.1.1. Instantiation of Intel® Stratix® 10 PCIe* Hard IP with Direct Memory Access

The Intel® Stratix® 10 GX FPGA Development Kit Reference Platform instantiates the Intel® Stratix® 10 PCIe* hard IP with direct memory access (DMA) to implement a host-to-device connection over PCIe* .

Dependencies

  • Intel® Stratix® 10 PCIe* hard IP core
  • Parameter Settings section of the Intel® Stratix® 10 Avalon® -MM DMA Interface for PCIe Solutions User Guide
Table 4.  Highlights of Intel® Stratix® 10 PCIe* Hard IP Parameter SettingsSet the parameters for the Intel® Stratix® 10 PCIe* hard IP in the parameter editor within the Intel® Quartus® Prime Pro Edition software.
Parameter(s) Setting
System Settings
Application interface type Avalon® -MM with DMA

This Avalon® Memory-Mapped ( Avalon® -MM) interface instantiates the embedded DMA of the PCIe® hard IP core.

Check the Enable Avalon-MM DMA option under Avalon-MM settings.

Hard IP mode

Gen3x8, Interface: 256-bit, 250 MHz

Number of Lanes: x8

Lane Rate: Gen3 (8.0 Gbps)

Avalon® -MM Settings
Export MSI/MSI-X conduit interfaces Enabled

Export the MSI interface in order to connect the interrupt sent from the kernel interface to the MSI.

Instantiate Internal Descriptor Controller Enabled

Instantiates the descriptor controller in the Avalon® -MM DMA bridge. Use the 128-entry descriptor controller that the PCIe* hard IP core provides.

Address width of accessible PCIe memory space 64 bits

This value is machine dependent. To avoid truncation of the MSI memory address, 64-bit machines should allot 64 bits to access the PCIe* address space.

Base Address Register (BAR) Settings
Base Address Registers (BARs) This design uses two BARs.

For BAR 0, set Type to 64-bit prefetchable memory. The Size parameter setting is disabled because the Instantiate Internal Descriptor Controller parameter is enabled in the Avalon® -MM system settings.

BAR 0 is only used to access the DMA Descriptor Controller, as described in the Intel® Stratix® 10 Avalon® -MM DMA for PCI Express section of the Intel® Stratix® 10 Avalon® -MM DMA Interface for PCIe* Solutions User Guide.

For Bar 4, set Type to 64-bit prefetchable memory, and set Size to 18 bits (256 KBytes).

BAR 4 is used to connect PCIe to the OpenCL kernel systems and other board modules.

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