Intel® FPGA SDK for OpenCL™: Intel® Stratix® 10 GX FPGA Development Kit Reference Platform Porting Guide

ID 683809
Date 3/28/2022
Document Table of Contents

2.6.1. Clocks

Several clock domains affect the Platform Designer hardware system of the Intel® Stratix® 10 GX FPGA Development Kit Reference Platform.

These clock domains include:

  • 100 MHz PCIe* clock
  • 116 MHz DDR4 clock
  • 50 MHz general clock (config_clk)
  • Kernel clock that can have any clock frequency

With the exception of the kernel clock, the s10_ref Reference Platform is responsible for the timing closure of these clocks. However, because the board design must clock cross all interfaces in the kernel clock domain, the board design also has logic in the kernel clock domain. It is crucial that this logic is minimal and achieves an Fmax higher than typical kernel performance.

Note: OpenCL S10 reconfigurable kernel clock generator (kernel_clk_gen) is the reconfigurable PLL that generates kernel_clk and kernel_clk2x for the kernel. You must specify the REF_CLK_RATE of the clock that you are passing to this configurable PLL. Leave the value of KERNEL_TARGET_CLOCK_RATE as 500.