R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.5.1.1. Transmit Signals

Table 43.  PIPE Direct EMIB Data Channel Transmit SignalsIn the signal names, X is the lane number and ranges from 0 to 15.
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_rxstandby_i Input Synchronous rxstandby signal pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txelecidle_i[3:0] Input One bit per two Symbols, for a maximum of 8 symbols. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_powerdown_i[1:0] Input PHY power state control signals pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_rate_i[2:0] Input

Gen1-5 rate change control signals:

000: Gen1

001: Gen2

010: Gen3

011: Gen4

100: Gen5

pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdetectrx_i Input Receiver detect control signal pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid1_i Input This signal qualifies txdata[63:32]. This is the TxValid signal per the PIPE Specification 5.1.1. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdatavalid0_i Input This signal qualifies txdata[31:0]. This is the TxValid signal per the PIPE Specification 5.1.1. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_txdata_i[63:0] Input Transmit data bus pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_pld_pcs_rst_n_i Input This is the PHY channel reset signal. It is an asynchronous signal. Async
lnX_pipe_direct_rxtermination_i Input Controls the presence of receiver terminations. This is a PIPE signal mainly intended for USB usage. Intel recommends driving this signal high (default).
  • 0 = Terminations removed.
  • 1 = Terminations present.
pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_pclkchangeack_i Input Asserted by the MAC when a PCLK rate change or, if required, width change is complete and stable. pipe_direct_pld_tx_clk_out_o
lnX_pipe_direct_tx_transfer_en_o Output This signal indicates when the EMIB is ready in PIPE mode. The soft IP controller must release the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signal out of reset after the per-lane lnX_pipe_direct_tx_transfer_en_o signal is asserted. pipe_direct_pld_tx_clk_out_o

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