R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.4.1.2.4.1. Completion Buffer Size

R-tile implements Completion (Cpl) buffers for header and data for each PCIe core. In Endpoint mode, when Completion credits are infinite, user application needs to manage the number of outstanding requests to prevent overflow and lost Completions.

Table 20.  Completion Buffer Size
Completion Buffer Depth Width
Port 0 Cpl header 572 N/A
Port 0 Cpl data 2048 256
Port 1 Cpl header 256 N/A
Port 1 Cpl data 1024 128
Port 2 Cpl header 128 N/A
Port 2 Cpl data 512 64
Port 3 Cpl header 128 N/A
Port 3 Cpl data 512 64

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