R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

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4.5.5. PIPE Direct Speed Change

In the PIPE Direct Data mode, the clock for the RX datapath is sourced from the PHY recovered clock (pipe_direct_pld_rx_clk_out_o). The PHY recovered clock changes frequency when the PHY trains from Gen1 to Gen5. During the PIPE Direct RX rate change, the following sequence needs to be adhered to.

The soft MAC first changes the rate or width if required. The PHY only asserts pipe_pclk_changeok after the MAC has made the changes. The MAC asserts pipe_pclk_changeack when the change is complete and stable. After the MAC asserts pipe_pclk_changeack, the PHY responds by asserting phystatus for one cycle and deasserting pclk_changeok at the same time as phystatus. The MAC deasserts pipe_pclk_changeack when pipe_pclk_changeok is sampled low.

As a reference, the following two timing diagrams illustrate the speed change from Gen1 to Gen5.
Note: Although the diagrams below illustrate a speed change from Gen1 to Gen5, the overall sequence applies to all speed changes. However, the final value of ln0_pipe_direct_rate_i in Step 1 varies depending on what the final speed is.
Figure 33. PIPE Direct Speed Change (Part 1)
Figure 34. PIPE Direct Speed Change (Part 2)
The steps shown in the diagrams are:
  1. The Soft IP controller changes the PIPE per-channel rate signal (ln0_pipe_direct_rate_i) to the IP from Gen1 to Gen5.
  2. The IP deasserts the PIPE RX reset status signal (ln_pipe_direct_reset_status_n_o) for each channel.
  3. The PIPE per-channel PCLK change OK and ACK signals (ln0_pipe_direct_pclkchangeok_o, ln0_pipe_direct_pclkchangeack_i) are asserted.
  4. The IP deasserts the PIPE per-channel RX CDR lock-to-reference signal (ln0_pipe_direct_cdrlockstatus_o).
  5. The IP sends the PIPE per-channel PHY status pulse (ln0_pipe_direct_phystatus_o) to the Soft IP controller.
  6. The PIPE per-channel TX data (ln0_pipe_direct_txdata_i) transfer from the Soft IP controller to the IP begins (at Gen5 rate).
  7. The IP asserts the PIPE per-channel RX CDR lock-to-data signal (ln0_pipe_direct_cdrlock2data_o).
  8. The PIPE per-channel RX output clock (ln0_pipe_direct_pld_rx_clk_out_o) from the IP to the Soft IP controller becomes active.
  9. The PIPE per-channel RX data (ln0_pipe_direct_pipe_rxdata_o) transfer from the IP to the Soft IP controller begins (at Gen5 rate).

Figure 35 and Figure 36 provide an illustration of the PIPE Direct mode TX and RX datapath signals.

Figure 35. PIPE Direct TX DatapathAt Gen1 and Gen2 speeds, only the 10 LSB bits from the lower segment of LnX_pipe_direct_txdata bus contain valid data. Bits [63:10] are don't-cares.
Figure 36. PIPE Direct RX DatapathAt Gen1 and Gen2 speeds, only the 10 LSB bits in the upper and lower segments of the LnX_pipe_direct_rxdata_o bus contain valid data. Bits [31:10] and [63:42] are don't-cares.