R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 683501
Date 10/06/2021
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives 7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers B. Root Port Enumeration C. Implementation of Address Translation Services (ATS) in Endpoint Mode D. Packets Forwarded to the User Application in TLP Bypass Mode
1. Introduction x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core Support Levels
1.1. Overview x
1.1.1. Standards and Specifications Compliance
2. IP Architecture and Functional Description x
2.1. Overview 2.2. PCIe Hard IP Mode 2.3. PIPE Direct Mode
2.2. PCIe Hard IP Mode x
2.2.1. Clocking 2.2.2. Reset 2.2.3. PCI Express Protocol Stack
2.2.3. PCI Express Protocol Stack x
2.2.3.1. PMA/PCS 2.2.3.2. Data Link Layer Overview 2.2.3.3. Transaction Layer Overview
2.3. PIPE Direct Mode x
2.3.1. Clocking 2.3.2. Reset 2.3.3. PIPE Layer
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Serial Data Interface 4.4. PCI Express Mode 4.5. PIPE Direct Mode
4.2. Clocks and Resets x
4.2.1. Clocks 4.2.2. Resets
4.4. PCI Express Mode x
4.4.1. Avalon® Streaming Interface 4.4.2. Precision Time Measurement (PTM) Interface 4.4.3. Interrupt Interface 4.4.4. Hard IP Reconfiguration Interface 4.4.5. Error Interface 4.4.6. Completion Timeout Interface 4.4.7. Configuration Intercept Interface 4.4.8. Power Management Interface 4.4.9. Hard IP Status Interface 4.4.10. Page Request Services (PRS) Interface 4.4.11. Function-Level Reset (FLR) Interface 4.4.12. SR-IOV VF Error Flag Interface 4.4.13. General Purpose VSEC Interface
4.4.1. Avalon® Streaming Interface x
4.4.1.1. TLP Header and Data Alignment for the Avalon® streaming RX and TX Interfaces 4.4.1.2. Credit Control 4.4.1.3. Avalon® Streaming RX Interface 4.4.1.4. Avalon® Streaming TX Interface 4.4.1.5. Tag Allocation
4.4.1.2. Credit Control x
4.4.1.2.1. Credit Interface - Data and Header 4.4.1.2.2. Credit Initialization 4.4.1.2.3. Credit Update/Release 4.4.1.2.4. RX Flow Control Interface 4.4.1.2.5. TX Flow Control Interface
4.4.1.2.4. RX Flow Control Interface x
4.4.1.2.4.1. Completion Buffer Size
4.4.1.4. Avalon® Streaming TX Interface x
4.4.1.4.1. Avalon® Streaming TX Interface tx_st_ready_o Behavior
4.4.3. Interrupt Interface x
4.4.3.1. Legacy Interrupts 4.4.3.2. MSI 4.4.3.3. MSI-X
4.4.3.3. MSI-X x
4.4.3.3.1. Implementing MSI-X Interrupts
4.4.8. Power Management Interface x
4.4.8.1. Endpoint D3Hot Entry 4.4.8.2. Endpoint D3Hot Exit
4.5. PIPE Direct Mode x
4.5.1. Data Signals 4.5.2. Message Channel 4.5.3. Deskew Channel 4.5.4. PIPE Direct Reset Sequence 4.5.5. PIPE Direct Speed Change 4.5.6. PIPE Lane Reset Staggering 4.5.7. Unused Lanes in PIPE Direct Mode 4.5.8. PIPE Direct Mode TX/RX Datapaths
4.5.1. Data Signals x
4.5.1.1. Transmit Signals 4.5.1.2. Receive Signals
5. Advanced Features x
5.1. PCIe Port Bifurcation and PHY Channel Mapping 5.2. Virtualization Support 5.3. TLP Bypass Mode
5.2. Virtualization Support x
5.2.1. SR-IOV Support 5.2.2. VirtIO Support
5.2.1. SR-IOV Support x
5.2.1.1. SR-IOV Supported Features List 5.2.1.2. Implementation 5.2.1.3. VF to PF Mapping 5.2.1.4. Function Level Reset (FLR)
5.2.1.2. Implementation x
5.2.1.2.1. VF Error Flag Interface (for x16/x8 Cores Only)
5.2.2. VirtIO Support x
5.2.2.1. VirtIO Supported Features List 5.2.2.2. Overview 5.2.2.3. Parameters 5.2.2.4. VirtIO PCI Configuration Access Interface 5.2.2.5. Registers
5.2.2.5. Registers x
5.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012) 5.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013) 5.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014) 5.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015) 5.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016) 5.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017) 5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018) 5.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019) 5.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A) 5.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F) 5.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030) 5.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031) 5.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032) 5.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033) 5.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034) 5.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035) 5.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036) 5.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037) 5.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038) 5.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039) 5.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A) 5.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
5.3. TLP Bypass Mode x
5.3.1. Overview 5.3.2. Register Settings for the TLP Bypass Mode 5.3.3. User Avalon Memory-mapped Interface 5.3.4. Avalon® Streaming Interface
5.3.2. Register Settings for the TLP Bypass Mode x
5.3.2.1. TLPBYPASS_ERR_EN (Address 0x1314) 5.3.2.2. TLPBYPASS_ERR_STATUS (Address 0x1310)
5.3.4. Avalon® Streaming Interface x
5.3.4.1. Configuration TLP 5.3.4.2. Transmit Interface 5.3.4.3. Receive Interface 5.3.4.4. Malformed TLP 5.3.4.5. ECRC
C. Implementation of Address Translation Services (ATS) in Endpoint Mode x
C.1. Sending Translated/Untranslated Requests C.2. Sending a Page Request Message from the Endpoint (EP) to the Root Complex (RC) C.3. Invalidating Requests/Completions
D. Packets Forwarded to the User Application in TLP Bypass Mode x
D.1. EP TLP Bypass Mode (Upstream) D.2. RC TLP Bypass Mode (Downstream)
1. Introduction
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode

4.5.3. Deskew Channel

In PIPE Direct mode, the PHY wrapper removes any lane-to-lane skew introduced while crossing the EMIB. A dedicated deskew marker is used for detecting and compensating for any multi-lane skew introduced by EMIB. The deskew logic can account for a maximum of up to 3 cycles of parallel skew.

Table 46.  EMIB TX Deskew Grouping for R-tile Topologies
PIPE Direct Tx Deskew Bundle Octet 1 Octet 0
Lane 15 Lane 14 Lane 13 Lane 12 Lane 11 Lane 10 Lane 9 Lane 8 Lane 7 Lane 6 Lane 5 Lane 4 Lane 3 Lane 2 Lane 1 Lane 0
1X16 Octet1_Dsk_0 Octet0_Dsk_0
2X8 Octet1_Dsk_0 Octet0_Dsk_0
4X4 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
8X2 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
16X1 No Tx Deskew
2X4; 1X8 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_0
4X2; 1X8 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_0
8X1; 1X8 No Tx Deskew Octet0_Dsk_0
1X8; 2X4 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
4X2; 2X4 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 Octet0_Dsk_2 Octet0_Dsk_0
8X1; 2X4 No Tx Deskew Octet0_Dsk_0 Octet0_Dsk_0
1X8; 4X2 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
2X4; 4X2 Octet1_Dsk_2 Octet1_Dsk_0 Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
8X1; 4X2 No Tx Deskew Octet0_Dsk_3 Octet0_Dsk_2 Octet0_Dsk_1 Octet0_Dsk_0
1X8; 8X1 Octet1_Dsk_0 No Tx Deskew
2X4; 8X1 Octet1_Dsk_2 Octet1_Dsk_0 No Tx Deskew
4X2; 8X1 Octet1_Dsk_3 Octet1_Dsk_2 Octet1_Dsk_1 Octet1_Dsk_0 No Tx Deskew

MAC to PHY (M2P) Signals

Table 47.  PIPE Direct EMIB Control Deskew Channel M2P Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_deskew_clear_0/1/2/3_i Input When asserted, the current tx_dsk_eval_done and tx_dsk_status are cleared. A new deskew evaluation is expected after the current status is cleared. This signal is asserted for two clock cycles. pipe_direct_pld_tx_clk_out_o

PHY to MAC (P2M) Signals

Table 48.  PIPE Direct EMIB Control Deskew Channel P2M Signals
Signal Name Direction Descriptions/Notes Clock Domain
lnX_pipe_direct_txdeskewmarker_i Input Tx Deskew marker used to deskew EMIB routings per bundle mode. This is a simple repeating pulse that provides a protocol-agnostic mechanism to detect EMIB channel skew and perform alignment. The marker fans out and appears on all bundle channels simultaneously once every 16 clock cycles. The deskew module looks for the deskew marker from each EMIB channel and adds delays on the early channels to compensate for the delays of the late channels. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_active_chans_o Output Indicates which channels received a deskew marker. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_o Output Value is latched upon an error, and held until the state machine is restarted via i_dsk_clear or async reset. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_monitor_err_status_[3:0]_o Output Indicates a deskew monitor error. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_status_[3:0]_o Output Indicates the deskew evaluation result. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_valid_[3:0]_o Output Indicates the deskew operation status. pipe_direct_pld_tx_clk_out_o
octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o Output Indicates the deskew process is complete. This signal is for debugging purpose. pipe_direct_pld_tx_clk_out_o
Note: octet#_pipe_direct_phy_dsk_status should be monitored only after octet#_pipe_direct_phy_dsk_valid is asserted.

After data from each EMIB channels are deskewed, the octet#_pipe_direct_phy_dsk_valid signals are asserted to indicate the deskew done status. In addition to the octet#_pipe_direct_phy_dsk_valid signals, the PIPE Direct interface provides octet#_pipe_direct_phy_dsk_eval_done and octet#_pipe_direct_phy_dsk_status signals to show the details of the deskew status. However, those signals are for debugging purpose only. User application logic should only rely on octet#_pipe_direct_phy_dsk_valid and should not send TX packets before this signal is asserted. The octet#_pipe_direct_deskew_clear signal can be used to clear the current deskew state to allow additional deskew evaluations. You can optionally monitor octet#_pipe_direct_phy_dsk_eval_done and octet#_pipe_direct_phy_dsk_status signals in the FPGA fabric to know if the deskew process has either completed successfully or failed.

After cold reset, user application logic needs to send a deskew marker every 16 clock cycles for the purpose of deskewing the data on the EMIB channels. The PHY deskew logic will run the deskew process every time it receives the deskew marker.

Level Two Title