Visible to Intel only — GUID: glk1602633525744
Ixiasoft
Visible to Intel only — GUID: glk1602633525744
Ixiasoft
4.5.3. Deskew Channel
In PIPE Direct mode, the PHY wrapper removes any lane-to-lane skew introduced while crossing the EMIB. A dedicated deskew marker is used for detecting and compensating for any multi-lane skew introduced by EMIB. The deskew logic can account for a maximum of up to 3 cycles of parallel skew.
PIPE Direct Tx Deskew Bundle | Octet 1 | Octet 0 | ||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Lane 15 | Lane 14 | Lane 13 | Lane 12 | Lane 11 | Lane 10 | Lane 9 | Lane 8 | Lane 7 | Lane 6 | Lane 5 | Lane 4 | Lane 3 | Lane 2 | Lane 1 | Lane 0 | |
1X16 | Octet1_Dsk_0 | Octet0_Dsk_0 | ||||||||||||||
2X8 | Octet1_Dsk_0 | Octet0_Dsk_0 | ||||||||||||||
4X4 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | ||||||||||||
8X2 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | ||||||||
16X1 | No Tx Deskew | |||||||||||||||
2X4; 1X8 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_0 | |||||||||||||
4X2; 1X8 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_0 | |||||||||||
8X1; 1X8 | No Tx Deskew | Octet0_Dsk_0 | ||||||||||||||
1X8; 2X4 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | |||||||||||||
4X2; 2X4 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | Octet0_Dsk_2 | Octet0_Dsk_0 | ||||||||||
8X1; 2X4 | No Tx Deskew | Octet0_Dsk_0 | Octet0_Dsk_0 | |||||||||||||
1X8; 4X2 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | |||||||||||
2X4; 4X2 | Octet1_Dsk_2 | Octet1_Dsk_0 | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | ||||||||||
8X1; 4X2 | No Tx Deskew | Octet0_Dsk_3 | Octet0_Dsk_2 | Octet0_Dsk_1 | Octet0_Dsk_0 | |||||||||||
1X8; 8X1 | Octet1_Dsk_0 | No Tx Deskew | ||||||||||||||
2X4; 8X1 | Octet1_Dsk_2 | Octet1_Dsk_0 | No Tx Deskew | |||||||||||||
4X2; 8X1 | Octet1_Dsk_3 | Octet1_Dsk_2 | Octet1_Dsk_1 | Octet1_Dsk_0 | No Tx Deskew |
MAC to PHY (M2P) Signals
Signal Name | Direction | Descriptions/Notes | Clock Domain |
---|---|---|---|
lnX_pipe_direct_deskew_clear_0/1/2/3_i | Input | When asserted, the current tx_dsk_eval_done and tx_dsk_status are cleared. A new deskew evaluation is expected after the current status is cleared. This signal is asserted for two clock cycles. | pipe_direct_pld_tx_clk_out_o |
PHY to MAC (P2M) Signals
Signal Name | Direction | Descriptions/Notes | Clock Domain |
---|---|---|---|
lnX_pipe_direct_txdeskewmarker_i | Input | Tx Deskew marker used to deskew EMIB routings per bundle mode. This is a simple repeating pulse that provides a protocol-agnostic mechanism to detect EMIB channel skew and perform alignment. The marker fans out and appears on all bundle channels simultaneously once every 16 clock cycles. The deskew module looks for the deskew marker from each EMIB channel and adds delays on the early channels to compensate for the delays of the late channels. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_active_chans_o | Output | Indicates which channels received a deskew marker. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_monitor_err_o | Output | Value is latched upon an error, and held until the state machine is restarted via i_dsk_clear or async reset. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_monitor_err_status_[3:0]_o | Output | Indicates a deskew monitor error. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_status_[3:0]_o | Output | Indicates the deskew evaluation result. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_valid_[3:0]_o | Output | Indicates the deskew operation status. | pipe_direct_pld_tx_clk_out_o |
octet#_pipe_direct_phy_dsk_eval_done_[3:0]_o | Output | Indicates the deskew process is complete. This signal is for debugging purpose. | pipe_direct_pld_tx_clk_out_o |
After data from each EMIB channels are deskewed, the octet#_pipe_direct_phy_dsk_valid signals are asserted to indicate the deskew done status. In addition to the octet#_pipe_direct_phy_dsk_valid signals, the PIPE Direct interface provides octet#_pipe_direct_phy_dsk_eval_done and octet#_pipe_direct_phy_dsk_status signals to show the details of the deskew status. However, those signals are for debugging purpose only. User application logic should only rely on octet#_pipe_direct_phy_dsk_valid and should not send TX packets before this signal is asserted. The octet#_pipe_direct_deskew_clear signal can be used to clear the current deskew state to allow additional deskew evaluations. You can optionally monitor octet#_pipe_direct_phy_dsk_eval_done and octet#_pipe_direct_phy_dsk_status signals in the FPGA fabric to know if the deskew process has either completed successfully or failed.
After cold reset, user application logic needs to send a deskew marker every 16 clock cycles for the purpose of deskewing the data on the EMIB channels. The PHY deskew logic will run the deskew process every time it receives the deskew marker.