R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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Document Table of Contents

4.1. Overview

There are four PCIe cores in R-tile. You can determine which core each interface in this section belongs to by looking at the prefixes in the signal names:
  • p0 : x16 core
  • p1 : x8 core
  • p2 : x4_0 core
  • p3 : x4_1 core
Note: The x4_0 core is not available in the 21.3 release of Intel® Quartus® Prime.

below shows the top-level signals of this IP. Note that the signal names in the figure will get the appropriate prefixes pn (where n = 0, 1, 2 or 3) depending on which of the supported topologies (x16, x8x8, x4x4x4x4) the R-tile Avalon® streaming IP for PCIe is in.

The only cases where the interface signal names do not get the pn prefixes are the interfaces that are common for all the cores, like clocks and resets.

Each of the cores has its own Avalon® streaming interface to the user logic in the FPGA fabric. The number of IP-to-User Logic interfaces exposed to the FPGA fabric are different based on the topologies:
Table 12.  IP to FPGA Fabric Interfaces Summary
Topology Avalon-ST Interface Count Data Width (each Interface) Header Width (each Interface) TLP Prefix Width (each Interface) Application Clock Frequency
Gen5 x16 EP/RP 1 1024-bit (four 256-bit segments) 512-bit (four 128-bit segments) 128-bit (four 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

Gen4 x16 EP/RP 1 1024-bit 512-bit 128-bit

250 MHz / 275 MHz / 300 MHz

Gen3 x16 EP/RP 1 1024-bit 512-bit 128-bit

250 MHz / 275 MHz / 300 MHz

Gen5 x8 x8 EP/RP 2 512-bit (two 256-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

Gen4 x8 x8 EP/RP 2 512-bit 256-bit 64-bit

250 MHz / 275 MHz / 300 MHz

Gen3 x8 x8 EP/RP 2 512-bit 256-bit 64-bit

250 MHz / 275 MHz / 300 MHz

Gen5 x4 x4 x4 x4 EP/RP (†) 4 (†) 256-bit (two 128-bit segments) 256-bit (two 128-bit segments) 64-bit (two 32-bit segments)

400 MHz / 425 MHz / 450 MHz / 475 MHz / 500 MHz

Gen4 x4 x4 x4 x4 EP/RP (†) 4 (†) 256-bit 256-bit 64-bit

250 MHz / 275 MHz / 300 MHz

Gen3 x4 x4 x4 x4 EP/RP (†) 4 (†) 256-bit 256-bit 64-bit

250 MHz / 275 MHz / 300 MHz

Note: (†) In the 21.3 release of Intel® Quartus® Prime, only a maximum of three x4 Ports (p0, p1 and p3) are available in RP mode since p2 (core x4_0) is not available. In EP mode, only two x4 Ports (p0 and p1) are available.

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