4.5.4. PIPE Direct Reset Sequence
In PIPE Direct mode, your application logic is responsible for managing most of the PHY reset sequence in the FPGA fabric.
- PERST# (pin_perst_n) deasserts the IP.
- The Soft IP controller asserts the PIPE per-channel reset (ln0_pipe_direct_pld_pcs_rst_n_i) input to the IP.
- The PIPE TX output clock (pipe_direct_pld_tx_clk_out_o) from the IP to the Soft IP controller becomes active.
- The fabric sector ready signal (ninit_done) from the FPGA fabric to the IP is asserted.
- The PIPE per-channel PHY status signal (ln0_pipe_direct_phystatus_o) from the IP to the Soft IP controller is deasserted.
- The PIPE per-channel PHY status signal (ln0_pipe_direct_phystatus_o), PIPE RX status signal (ln0_pipe_direct_rxstatus_o) from the IP to the Soft IP controller are pulsed by the IP indicating RX detection.
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