22.214.171.124. Tag Allocation
The R-Tile PCIe Hard IP supports the 10-bit tag Requester capability in the x16 Controller (Port 0) only. It supports up to 768 outstanding Non-Posted Requests (NPRs) with valid tag values ranging from 256 to 1023.
The x8 (Port 1) and x4 Controllers (Port 2/3) don’t support the 10-bit tag Requester capability, although they support the 10-bit Completer capability. Both x8 and x4 Controllers can allow up to 512 outstanding NPRs with valid tag values ranging from 0 to 511.
- 8-bit tags : 0 - 63
- 10-bit tags : 320 - 511, 576 - 1023
Note that all PFs and their associated VFs share the same tag space. This means that different PFs and VFs cannot have outstanding tags having the same tag values.
In the TLP bypass mode, there is no restriction on the tag allocation since the R-Tile PCIe Hard IP does not do any tag management. Hence, 10-bit tags can be used without any restriction across all the cores.
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