R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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Document Table of Contents

7. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.10.06 21.3 3.0.0 Removed the section ECRC due to missing information on the register offsets for the ECRC or LCRC counters.
2021.10.04 21.3 3.0.0

Updated the block diagrams in the PCI Express Mode and PIPE Direct Mode sections to match the interface signals on the 21.3 block symbol for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express.

Added a Note to the Avalon Streaming TX Interface section stating that for this interface, the SOP can only be sent on segments 0 and 2.

Added the Root Port Enumeration Appendix chapter.

2021.07.12 21.2 2.0.0 Initial release.

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