4.4.8. Power Management Interface
Software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management output signals indicate the current power state. The IP core supports the two mandatory power states: D0 (full power) and D3Hot. It does not support the optional D1 and D2 low-power states.
The correspondence between the device power states (D states) and link power states (L states) is as follows:
|Device Power State||Link Power State|
|D1 (not supported)||L1|
|D2 (not supported)||L1|
|D3Hot||L1, L2/L3 Ready|
R-tile does not support ASPM in the 21.3 release of Intel® Quartus® Prime.
|Signal Name||Direction||Description||Clock Domain||EP/RP/BP|
|pm_curnt_state_o[7:0]||O||Indicates the current power state.
|O||Power management D-state for each function.
|I||The application logic asserts this signal for one cycle to wake up the Power Management Capability (PMC) state machine from a D1, D2, or D3 Hot power state. Upon wake-up, the IP core sends a PM_PME message. This signal needs to be asserted for one clock cycle.||slow_clk||EP/BP|
|I||The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. The app_ready_entr_l23_i signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready). The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active. This is a level-sensitive signal.||slow_clk||EP/BP|
|apps_pm_xmt_turnoff_i||I||This signal is a pulse input. It is a request from the Application Layer to generate a PM_Turn_Off message. The Application Layer must assert this signal for one clock cycle. The IP core does not return an acknowledgement or grant signal. The Application Layer must not pulse the same signal again until the previous message has been transmitted.||slow_clk||RP|
|app_init_rst_i||I||The Application Layer uses this signal to request a hot reset to downstream devices. The hot reset request will be sent when a single-cycle pulse (~20ns) is applied to this pin.||Asynchronous||RP|
When asserted, the PCIe Hard IP responds to Configuration TLPs with a CRS (Configuration Retry Status) if it has not already responded to a Configuration TLP with non-CRS status since the last reset. The user application can use this signal to hold off on enumeration. This input is not used for Root Ports.
This bus must be enabled with k_pld_crs_en. It applies to both Endpoints when the Hard IP is configured as 2x8.
The x4 cores (Ports 2 and 3) also have these pins but they are not used and need to be driven to zero.
|app_xfer_pending_i||I||This signal does not prevent an entry to the low-power L1 state, but causes an immediate exit from L1.||Asynchronous||EP/RP/BP|
The following table shows the support for L2/L3 states in R-tile.
|EP/BP UP||RP/BP DN|
|L2 exit||Host to initiate or Cold Reset||Cold Reset|
|L3 exit||Cold Reset||Cold Reset|
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