4.4.2. Precision Time Measurement (PTM) Interface
Following are the PTM interface signals between the IP and the FPGA core fabric. Only x16 and x8 PCIe modes are supported. The accuracy supported by this interface is +/-50 ns.
|pX_ptm_context_valid_o||Output||When this signal is asserted, it indicates that the value present on the ptm_time bus is valid. Hardware will deassert this bit whenever a PTM dialogue is requested and an update is in progress.||EP/RP/BP||coreclkout_hip|
|pX_clk_updated_o||Output||This one clock pulse is an indication that the PTM dialogue has completed and the results of that operation have been driven on the ptm_time bus.||EP/RP/BP||coreclkout_hip|
|pX_ptm_local_clock_o[63:0]||Output||This bus contains the calculated master time at t1’ as indicated in the PCIe spec plus any latency to do the calculation and to drive the value to the requester.||EP/RP/BP||coreclkout_hip|
|pX_ptm_manual_update_i||Input||Asserted high for one coreclkout_hip clock when the user application wants to request a PTM handshake to get a snapshot of the latest time.||EP/RP/BP||coreclkout_hip|
For more details, refer to Section 6.22 Precision Time Measurement (PTM) Mechanism of the PCI Express* Base Specification Revision 5.0 Version 1.0.
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