R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)

This register indicates where the structure begins relative to the base address associated with the BAR. The alignment requirements of the offset are indicated in each structure-specific section.

Table 62.  VirtIO Notifications BAR Offset Register
Bit Location Description Access Type Default Value
31:0 BAR Offset RO Settable through the IP Parameter Editor

Did you find the information on this page useful?

Characters remaining:

Feedback Message