4.5.8. PIPE Direct Mode TX/RX Datapaths
Figure 37 below shows the behavior for the transitions required for the TX and RX to start a data transfer on lane 0. The behavior below applies to any PCIE controller which is in compliance with the PIPE specification.
- The TX output clock (pipe_direct_pld_tx_clk_out_o) from the IP to the Soft IP controller is active.
- The IP asserts the PIPE per-channel TX data transfer output signal (ln0_pipe_direct_tx_transfer_en_o).
- The PIPE per-channel TX data (ln0_pipe_direct_txdata_i) transfer from the Soft IP controller to the IP begins.
- The IP asserts the PIPE per-channel RX CDR lock-to-data signal (ln0_pipe_direct_cdrlock2data_o).
- The PIPE per-channel RX output clock (ln0_pipe_direct_pld_rx_clk_out_o) from the IP to the Soft IP controller becomes active.
- The PIPE per-channel RX data (ln0_pipe_direct_rxdata_o) transfer from the IP to the Soft IP controller begins.
Application logic needs to wait for the assertion of ln_pipe_direct_reset_status_n_o to sample Rx data.
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