R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.4.1.1. TLP Header and Data Alignment for the Avalon® streaming RX and TX Interfaces

The TLP prefix, header and data are sent and received on the Avalon® streaming TX and RX interfaces. There are four Avalon® streaming TX/RX interfaces corresponding to the four PCIe cores. The signal names on these interfaces are prefixed with "p0" for the x16 core, "p1" for the x8 core, "p2" for the x4_0 core and "p3" for the x4_1 core.

Each of these interfaces can contain up to four segments. The signal names for these segments are notated with *_st0_*, *_st1_*, *_st2_* and *_st3_*.

A Start of Packet (SOP) symbol demarcates the start of a packet. A command with or without data is terminated by an End of Packet (EOP) symbol. An EOP happening on the st0, st1, st2 or st3 segment implies that the last data with data valid = 1 is located on the corresponding data bus.

A command without data is qualified by a header valid indicator. A command with data is qualified by a data valid indicator. There is also a prefix valid indicator to qualify a TLP Prefix.

If a global valid signal is required for backward compatibility to P-tile, the header valid ORed with data valid will provide the global valid indicator.

This is defined to enable pipelined Header/Prefix and Data transfers to meet the bandwidth target. For example, while transferring the Data for one TLP, the Header and Prefix for the next TLP can also be transferred.

Figure 19. Generic TLP Format

The Avalon® streaming Header and TLP Prefix bus packet format follows the TLP packet format as defined by the PCIe specification for Memory, Configuration and Message TLPs. Refer to Figure 20 and Figure 21 below for more details.

In the R-tile Parameter Editor, there is a checkbox labeled PCIe Header format (in the PCIe Avalon® Settings tab) that allows you to specify whether the Header will follow the Big Endian format or Little Endian format. If this checkbox is not enabled, the Header follows the Little Endian format as shown in Figure 20 (note that the diagram shows the Prefix, Header and Data for one segment of the Avalon® streaming interface, not the whole interface):

Figure 20. TLP Prefix, Header and Data when PCIe Header Format Checkbox is Disabled

If the PCIe Header format checkbox is enabled, the Header follows the Big Endian format as shown in Figure 21:

Figure 21. TLP Prefix, Header and Data when PCIe Header Format Checkbox is Enabled
Table 17.  IP to FPGA Fabric Interface Summary
Configuration Link Rate Width Mode Header Data Application Clock Frequency (MHz)
x16 Gen5 Double-Width H3[127:0], H2[127:0], H1[127:0], H0[127:0] D3[255:0], D2[255:0], D1[255:0], D0[255:0] 400 - 500
Gen4 Double-Width H3[127:0], H2[127:0], H1[127:0], H0[127:0] D3[255:0], D2[255:0], D1[255:0], D0[255:0] 250 - 300
Gen3 Double-Width H3[127:0], H2[127:0], H1[127:0], H0[127:0] D3[255:0], D2[255:0], D1[255:0], D0[255:0] 250 - 300
x8x8 Gen5 Double-Width H1[127:0], H0[127:0] D1[255:0], D0[255:0] 400 - 500
Gen4 Double-Width H1[127:0], H0[127:0] D1[255:0], D0[255:0] 250 - 300
Gen3 Double-Width H1[127:0], H0[127:0] D1[255:0], D0[255:0] 250 - 300
x4x4x4x4 Gen5 Double-width H1[127:0], H0[127:0] D1[127:0], D0[127:0] 400 - 500
Gen4 Double-width H1[127:0], H0[127:0] D1[127:0], D0[127:0] 250 - 300
Gen3 Double-width H1[127:0], H0[127:0] D1[127:0], D0[127:0] 250 - 300
Note:
  • For the PCIe x16 configuration in double-width mode, the H2 TLP header is only allowed if H0 and H1 (also D0 and D1) have been used.
  • Single-width modes are not available in the 21.3 release of Intel® Quartus® Prime.
  • For x16 mode, an SOP can happen only on segment 0 (st0) or segment 2 (st2) for the TX Avalon streaming interface.

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