R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.4.1. Avalon® Streaming Interface

The R-tile PCIe Hard IP provides an Avalon® Streaming-like interface with separate header and data to improve the bandwidth utilization.

The Avalon® Streaming interface has different data bus widths depending on the link width configuration of the PCIe IP.

Table 16.   Avalon® Streaming Interface Data and Header Bus Widths
Rate PCIe Link Width Data Width (Bits) Header Width (Bits) TLP Prefix Width (Bits)
Gen5 x16 1024 (4 x 256) 512 (4 x 128) 128 (4 x 32)
x8 512 (2 x 256) 256 (2 x 128) 64 (2 x 32)
x4 256 (2 x 128) 256 (2 x 128) 64 (2 x 32)

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