R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.5.7. Unused Lanes in PIPE Direct Mode

In PIPE Direct mode, user logic is responsible for driving the lnX_pipe_direct_powerdown_i[1:0] to 2’b11 in the FPGA core fabric for those unused lanes. Upon entering user mode followed by the deassertion of ln0_pipe_direct_pld_pcs_rst_n_i by the user control core logic, the unused PHY will transition to P2 pstate.

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