R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

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2.2.2. Reset

There is only one PERST# (pin_perst_n) pin on R-tile. Therefore, toggling pin_perst_n will affect the entire R-tile. If the R-tile x16 port is bifurcated into two x8 Endpoints, toggling pin_perst_n will affect both x8 Endpoints. To reset each port individually, use the in-band mechanism such as Hot Reset and the Function-Level Reset (FLR). Following are the guidelines for implementing the R-tile pin_perst_n reset signal:
  • pin_perst_n is a "power good" indicator from the associated power domain (to which R-tile is connected). Also, it shall qualify that both the R-tile refclk0 and refclk1 are stable. If one of the reference clocks becomes stable later, deassert pin_perst_n after this reference clock becomes stable.
  • pin_perst_n assertion is required for proper Autonomous R-tile functionality. In Autonomous mode (enabled by default), R-tile can successfully link up upon the release of pin_perst_n regardless of the FPGA fabric configuration and will send out CRS (Configuration Retry Status) until the FPGA fabric is configured and ready.
  • To prevent potential device degradation, the pin_perst_n signal must not be held active if power is supplied to the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express when the FPGA is in user mode. If the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express is planned to be used but not in the early phases of your design cycle, you must configure it in BTI mode using the following qsf asigment:

    set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON

  • pin_perst_n assertion should be avoided during a functional-level reset or before a functional-level reset is completed since this could impact the link training process. In case this occurs, a cold reset would be required to properly complete the link training process.

The following is an example where a single PERST# (pin_perst_n) is driven with independent refclk0 and refclk1. In this example, the add-in card (FPGA and Soc) is powered up first. R-tile refclk0 is fed by the on-board free-running oscillator. R-tile refclk1 driven by the Host becomes stable later. Hence, the PERST# is connected to the Host.

Figure 5. Single PERST# Connection in Bifurcated 2x8 Mode