22.214.171.124. Receive Signals
|Signal Names||Direction||Descriptions/Notes||Clock Domain|
|lnX_pipe_direct_rxdatavalid1_o||Output||This signal qualifies rxdata[63:32]. This is the RxValid signal per the PIPE Specification 5.1.1.||lnX_pipe_direct_pld_rx_clk_out_o|
|lnX_pipe_direct_rxdatavalid0_o||Output||This signal qualifies rxdata[31:0]. This is the RxValid signal per the PIPE Specification 5.1.1.||lnX_pipe_direct_pld_rx_clk_out_o|
|lnX_pipe_direct_rxdata_o[63:0]||Output||Receive data bus||lnX_pipe_direct_pld_rx_clk_out_o|
|lnX_pipe_direct_rxelecIdle_o||Output||This signal indicates the receiver detection of an Electrical Idle. It is an asynchronous signal.||Async|
Indicates whether the PHY is active or in standby mode.
This signal is asserted by the PHY when it is ready for the MAC to change the clock rate.
Reflects the state of the high-speed receiver. A 1 on this bit indicates Rx is detected.
|lnX_pipe_direct_phystatus_o||Output||Indicates the completion of several PHY functions including stable PCLK, after reset deassertion, power management state transitions, rate change and receiver detection.||pipe_direct_pld_tx_clk_out_o|
This is the Receiver CDR lock indicator.
If this signal is deasserted when it is expected to be asserted, it indicates a fault condition and the receiver should be reset.
This is the Receiver CDR data lock indicator.
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