R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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5.3.3. User Avalon Memory-mapped Interface

For more details on the signals in this interface, refer to the section Hard IP Reconfiguration Interface.

The majority of the PCIe standard registers are implemented in the user’s logic outside of the R-tile Avalon® -ST IP.

However, the following registers still remain inside the R-tile:
  • Power management capability
  • PCI Express capability
  • Secondary PCI Express capability
  • Data link feature extended capability
  • Physical layer 16.0 GT/s and 32.0 GT/s extended capabilities
  • Lane margining at the receiver extended capability
  • Advanced error reporting capability

The application can only access PCIe controller registers through the User Avalon® -MM interface.

Table 81.  Capability Registers to be Updated by the Application Logic via the User Avalon-MM Interface
Capability Comments
Power Management Capability Need to write back since it is required to trigger a PCI-PM entry.
PCI Express Capability All the PCIe capabilities, control and status registers are for configuring the device. Write-back is required.
Secondary PCI Express Capability Secondary PCIe Capability is required for configuring the device.
Data Link Feature Extended Capability Data Link Capability is device specific.
Physical Layer 16.0 GT/s Extended Capability Physical Layer 16G Capability is device specific.
Lane Margining at the Receiver Extended Capability Margining Extended Capability is device specific.
Advanced Error Reporting Capability Write-back to error status registers is required for TLP Bypass.

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