R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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4.4.1.3. Avalon® Streaming RX Interface

The Application Layer receives data from the Transaction Layer of the PCI Express IP core over the Avalon® Streaming RX interface. The application must assert rx_st_ready_i before transfers can begin. For R-tile, the rx_st_ready_i has to be always high. The buffer control in user logic needs to be handled by credit-based control.

This interface supports four rx_st_sop_o signals and four rx_st_eop_o signals per cycle when the R-Tile IP is operating in a x16 configuration. It also does not follow a fixed latency between rx_st_ready_i and rx_st_valid_o as specified by the Avalon® Interface Specifications.

The x16 core provides four segments with each one having 256 bits of data (rx_st_data_o[255:0]), 128 bits of header (rx_st_hdr_o[127:0]), and 32 bits of TLP prefix (rx_st_ prfx_o[31:0]). If this core is configured in the 1x16 mode, four segments are used, so the data bus becomes a 1024-bit bus with four rx_st_data_o[255:0]. The start of packet can appear in the any of the segments, as indicated by the rx_st_sop_o signal in each segment.

If this core is configured in the 2x8 mode, there are still four Avalon® Streaming segments if the core IP is set up in double-width mode.

Parity generation is done via a 32:1 XOR (i.e. there is one parity bit for every 32 data, header or prefix bits).

Table 22.  Avalon Streaming RX Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_rx_stN_data_o[W:0] where

X = 0,1,2,3 (IP core number) and W varies based on the core. Refer to for more details.

N = 0,1,2,3 (segment number)

Output This is the Receive data bus. The Application Layer receives data from the Transaction Layer of the IP core on this bus. EP/RP/BP coreclkout_hip
pX_rx_stN_hdr_o[127:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output This is the received header, which follows the TLP header format of the PCIe specifications. EP/RP/BP coreclkout_hip
pX_rx_stN_prefix_o[31:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

This is the first TLP prefix received, which follows the TLP prefix format of the PCIe specifications. PASID is supported.

These signals are valid when the corresponding rx_st_sop_o is asserted.

The TLP prefix uses a Big Endian implementation (i.e, the Fmt field is in bits [31:29] and the Type field is in bits [28:24]).

If no prefix is present for a given TLP, that dword (including the Fmt field) is all zeros.

EP/RP/BP coreclkout_hip
pX_rx_stN_sop_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Signals the first cycle of the TLP when asserted in conjunction with the corresponding bit of rx_stN_valid_o.

rx_stN_sop_o: When asserted, signals the start of a TLP on rx_stN_data_o[255:0].

For example, when asserted, rx_st2_sop_o signals the start of a TLP on rx_st2_data_o[255:0].

EP/RP/BP coreclkout_hip
pX_rx_stN_eop_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Signals the last cycle of the TLP when asserted in conjunction with the corresponding bit of rx_stN_valid_o.

rx_stN_eop_o: When asserted, signals the end of a TLP on rx_stN_data_o[255:0].

For example, when asserted, rx_st2_eop_o signals the end of a TLP on rx_st2_data_o[255:0].

EP/RP/BP coreclkout_hip
pX_rx_stN_dvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_data_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_hvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_hdr_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_pvalid_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output These signals qualify the rx_stN_prefix_o signals going into the Application Layer. EP/RP/BP coreclkout_hip
pX_rx_stN_data_par_o[Z:0] where

X = 0,1,2,3 (IP core number) and Z varies based on the core.

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_data_o. EP/RP/BP coreclkout_hip
pX_rx_stN_hdr_par_o[3:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_hdr_o. EP/RP/BP coreclkout_hip
pX_rx_stN_prefix_par_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output Parity signals for rx_stN_prefix_o. EP/RP/BP coreclkout_hip
pX_rx_st_ready_i Input Indicates the Application Layer is ready to accept data. This signal should always be set to 1. The Flow Control on the RX side is handled through the Credit Control Interface. EP/RP/BP coreclkout_hip
pX_rx_stN_empty_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specifies the number of dwords that are empty during cycles when the rx_stN_eop_o signals are asserted. These signals are not valid when the rx_stN_eop_o signals are not asserted.

EP/RP/BP coreclkout_hip
pX_rx_stN_bar_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the BAR for the TLP being output.

These outputs are valid when both rx_stN_sop_o and rx_stN_valid_o are asserted.

EP/RP coreclkout_hip
pX_rx_stN_vfactive_o where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

When asserted, these signals indicate that the received TLP is targeting a virtual function. When these signals are deasserted, the received TLP is targeting a physical function and the rx_stN_pfnum_o signals indicate the function number.

These signals are valid when the corresponding rx_stN_sop_o is asserted.

EP/RP coreclkout_hip
pX_rx_stN_vfnum_o[10:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the target VF number for the received TLP. The application uses this information for both request and completion TLPs. For a completion TLP, these bits specify the VF number of the requester for this completion TLP.

These signals are valid when rx_stN_vf_active_o and the corresponding rx_stN_sop_o are asserted.

EP/RP coreclkout_hip
pX_rx_stN_pfnum_o[2:0] where

X = 0,1,2,3 (IP core number)

N = 0,1,2,3 (segment number)

Output

Specify the target physical function number for the received TLP.

These signals are valid when the corresponding rx_stN_sop_o is asserted.

EP/RP coreclkout_hip
Figure 24 below shows the timings for signals on this interface:
  1. p0_rx_st_ready_i must be set to high.
  2. The start of the first TLP arrives in segment 1 when p0_rx_st1_sop_o is asserted.
    1. p0_rx_st1_dvalid_o is also asserted.
  3. The end of the first TLP is in segment 2 as denoted by the assertion of p0_rx_st2_eop_o.
    1. p0_rx_st2_dvalid_o is also asserted.
    2. p0_rx_st2_empty_o indicates the number of dwords that are not valid for this first TLP.
  4. Data and header are segment-aligned. The header for the first TLP is also on segment 1.

The next TLP arrives in the next clock cycle in segment 1 and finishes in segment 0.

Figure 24.  Avalon® Streaming RX Interface Timings

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