R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4. Interfaces

This section focuses mainly on the signal interfaces that the R-tile IP for PCIe uses to communicate with the Application Layer in the FPGA fabric core. However, it also briefly covers the Serial Data Interface, which allows the IP to communicate with the link partner across the PCIe link.

Did you find the information on this page useful?

Characters remaining:

Feedback Message