R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.1. Overview

R-tile is an FPGA companion tile that supports PCI Express* configurations up to Gen5 x16 in Endpoint (EP), Root Port (RP) and Transaction Layer Packet (TLP) Bypass modes. Gen3, Gen4 and Gen5 configurations are natively supported. R-tile also supports up to 16 SerDes channels through a PHY Interface for PCI Express (PIPE) v5.1.1 in SerDes Architecture mode.

R-tile serves as a companion tile for the Intel® Agilex™ devices.