R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

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Document Table of Contents

1.1.1. Standards and Specifications Compliance

  • PCI Express Base Specification Revision 5.0, Version 1.0
  • Single Root I/O Virtualization and Sharing Specification, Revision 1.1
  • Address Translation Services, Revision 1.1
  • Virtual I/O Device (VIRTIO) Version 1.0
  • PHY Interface for PCI Express Specification, Version 5.1.1
    Note: This interface is directly accessible when the IP is in PIPE mode.