R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

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Document Table of Contents Endpoint D3Hot Entry

The following sequence describes the D3 entry procedure. All transmissions on the Avalon Streaming TX and RX interfaces must have completed before the R-Tile PCIe IP core can begin the L1 request (Enter_L1 DLLP). In addition, the RX buffer must be empty and the app_xfer_pending_i signal must be deasserted.
  1. Software on the host side writes the Power Management Control register to request the entry to D3Hot state.
  2. The endpoint stops transmitting requests when it has been taken out of D0. Application logic can use the pm_dstate_o signal to monitor the current D state.
  3. The link transitions to L1. Application logic can use the pm_curnt_state_o signal to monito the current L state.