R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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2.3.3. PIPE Layer

R-tile supports up to 16 SerDes channels through a PHY Interface for PCI Express (PIPE) v5.1.1 in SerDes Architecture mode, with 64/80 bits available to the fabric across the EMIB interface. For more details, refer to Data Signals. The R-tile PIPE Serdes mode does not include the PCS layer. You must implement the PCS layer (including the 8b/10b, 128b/130b encoding/decoding, elastic buffer, etc.) in the FPGA fabric using the soft IP controller.

The figure below shows the block diagram of the R-tile in PIPE Direct mode:

Figure 12. R-tile Avalon® -ST IP for PCI Express in PIPE Direct Mode

Refer to the PIPE 5.1.1 spec for more information on the PIPE SerDes architecture.

The R-Tile Avalon® -ST IP for PCI Express configured in PIPE Direct mode contains a Physical Medium Attachment (PMA) block for handling the Physical layer (PHY) packets. The PMA receives and transmits high-speed serial data on the serial lanes.

The R-tile PMA consists of two octets. Each octet contains a pair of transmit PLLs and eight SerDes lanes capable of running up to 32 GT/s to perform the various TX and RX functions.

The Slow PLL generates the required transmit clocks for Gen1/Gen2 speeds, while the Fast PLL generates the required clocks for Gen3/Gen4/Gen5 speeds.

The PMA performs functions such as serialization/deserialization, clock data recovery, and analog front-end functions such as Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE) and transmit equalization.

The transmitter consists of a 3-tap equalizer with one tap of pre-cursor, one tap of main cursor and one tap of post-cursor.

The receiver consists of attenuation (ATT), CTLE, Voltage gain amplifier (VGA) and a DFE blocks that are adaptive for Gen3/Gen4/Gen5 speeds. For PIPE mode, the third-party IP controller will perform the lane margining capability. Timing margining capabilities/parameters are as described in PMA/PCS.

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