R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021

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Document Table of Contents ECRC

In TLP Bypass mode, the R-tile Avalon® Streaming IP for PCIe does not check the ECRC for received TLPs nor generate the ECRC for transmitted TLPs. However, you can configure the IP to strip the ECRC from the TLP payload (when the TD bit is set) by enabling the Strip ECRC option in the PCIeN Configuration, Debug and Extension Options tab. Note that this option is only available in this tab when the IP is put in TLP Bypass mode (by choosing either the Upstream or Downstream option for the Port Mode parameter in the Top-Level Settings tab. Note that with the Strip ECRC option enabled, there is no mechanism to detect an ECRC error from the application logic.

Figure 43. Strip ECRC Option