R-tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/06/2021
Public

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2.3. PIPE Direct Mode

In PIPE Direct mode, you are responsible for implementing the Transaction Layer, Data Link Layer and the MAC (which includes the 128b/130b Encoder/Decoder block and the Elastic Buffer) in your application logic in the FPGA fabric. Only the PHY layer inside the R-tile IP for PCIe is active as shown in the following figure.

Figure 9. PIPE Direct Mode Top-Level Block Diagram

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