External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

14.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer

The Signal Tap II logic analyzer shows read and write activity in the system.

For more information about using the Signal Tap II logic analyzer, refer to the Design Debugging Using the Signal Tap  II Embedded Logic Analyzer chapter in volume 3 of the Quartus® Prime Handbook

To add the Signal Tap II logic analyzer, follow these steps:

  1. On the Tools menu click Signal Tap II Logic Analyzer .
  2. In the Signal Configuration window next to the Clock box, click (Browse Node Finder).
  3. Type the memory interface system clock (typically * phy_clk) in the Named box, for Filter select Signal Tap II: presynthesis and click List.
  4. Select the memory interface clock that is exposed to the user logic.
  5. Click OK.
  6. Under Signal Configuration, specify the following settings:
    • For Sample depth, select 512
    • For RAM type, select Auto
    • For Trigger flow control, select Sequential
    • For Trigger position, select Center trigger position
    • For Trigger conditions , select 1
  7. On the Edit menu, click Add Nodes.
  8. Search for specific nodes that you want to monitor, and click Add.
    Note: Signal Tap can probe only nodes that are exposed to FPGA core logic. Refer to pin descriptions for help in deciding which signals to monitor.
  9. Decide which signal and event you want to trigger on, and set the corresponding trigger condition.
  10. On the File menu, click Save, to save the Signal Tap II . stp file to your project.
    Note: If you see the message Do you want to enable Signal Tap II file “stp1.stp” for the current project, click Yes.
  11. After you add signals to the Signal Tap II logic analyzer, recompile your design by clicking Start Compilation on the Processing menu.
  12. Following compilation, verify that Timing Analyzer timing analysis passes successfully.
  13. Connect the development board to your computer.
  14. On the Tools menu, click Signal Tap II Logic Analyzer.
  15. Add the correct <project_name>.sof file to the SOF Manager:
    1. Click ... to open the Select Program Files dialog box.
    2. Select <your_project_name>.sof.
    3. Click Open.
    4. To download the file, click the Program Device button.
  16. When the example design including Signal Tap II successfully downloads to your development board, click Run Analysis to run once, or click Autorun Analysis to run continuously.