External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

7.2.1. Equations for DDR4 Board Skew Parameters

Table 261.  Board Skew Parameter Equations
Parameter Description/Equation
Maximum CK delay to DIMM/device The delay of the longest CK trace from the FPGA to any DIMM/device.
Where n is the number of memory clock and r is the number rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in each rank DIMM, the maximum CK delay is expressed by the following equation:
Maximum DQS delay to DIMM/device The delay of the longest DQS trace from the FPGA to the DIMM/device.
Where n is the number of DQS and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQS delay is expressed by the following equation:
Average delay difference between DQS and CK The average delay difference between the DQS signals and the CK signal, calculated by averaging the longest and smallest DQS delay minus the CK delay. Positive values represent DQS signals that are longer than CK signals and negative values represent DQS signals that are shorter than CK signals. The Quartus Prime software uses this skew to optimize the delay of the DQS signals for appropriate setup and hold margins.
Where n is the number of memory clock,