External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.2.1. DQS Tracking

The DQS Tracking feature tracks read capture clock/strobe timing variation over time, for improved read capture I/O timing. Sufficient samples are required to confirm the variation and to adjust the DQS-enable position to maintain adequate operating margins.
DQS tracking is enabled for QDRII/II+/II+ Xtreme,QDR-IV, and RLDRAM 3 protocols. For QDRII/II+/II+ Xtreme, QDR-IV, and RLDRAM 3, the circuity does not require specific commands to initiate the tracking, because the read capture clock/strobe is free-running. For these protocols, tracking occurs constantly and automatically when the circuitry is enabled. DQS tracking is not available for DDR3, DDR4, and LPDDR3 protocols.