External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

8.4. QDR II/II+/II+ Xtreme Board Design Guidelines

The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR II, QDR II+, or QDR II+ Xtreme SRAM interface in your system.
Note: In the following topics, QDR II SRAM refers to QDR II, QDR II+, and QDR II+ Xtreme SRAM unless stated otherwise.

The following topics focus on the following key factors that affect signal integrity:

  • I/O standards
  • QDR II SRAM configurations
  • Signal terminations
  • Printed circuit board (PCB) layout guidelines

I/O Standards

QDR II SRAM interface signals use one of the following JEDEC* I/O signaling standards:

  • HSTL-15—provides the advantages of lower power and lower emissions.
  • HSTL-18—provides increased noise immunity with slightly greater output voltage swings.