External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

14.5.10. Debugging Checklist

The following checklist is a good starting point when debugging an external memory interface.
Table 398.  Checklist



Try a different fit.

Check IP parameters at the operating frequency (tMRD, tWTR for example).

Ensure you have constrained your design with proper timing deration and have closed timing.

Simulate the design. If it fails in simulation, it shall fail in hardware.

Analyze timing.

Place and assign RZQ (OCT).

Measure the power distribution network (PDN).

Measure signal integrity.

Measure setup and hold timing.

Measure FPGA voltages.

Vary voltages.

Heat and cool the PCB.

Operate at a lower or higher frequency.

Check board timing and trace Information.

Check LVDS and clock sources, I/O voltages and termination.

Check PLL clock source, specification, and jitter.

Retarget to a smaller interface width or a single bank.