External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

13.4.7. Frequency of Operation

Certain frequencies of operation give you the best possible latency based on the memory parameters. The memory parameters you specify through the parameter editor are converted to clock cycles and rounded up.

In most cases, the frequency and parameter combination is not optimal. If you are using a memory device that has tRCD = 15 ns and running the interface at 1200 MHz, you get the following results:

  • For quarter-rate implementation (tCk = 3.33 ns):

    tRCD convert to clock cycle = 15/3.33 = 4.5, rounded up to 5 clock cycles or 16.65 ns.