External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents emif_usr_clk_sec for DDR4

User clock interface (for the secondary interface in ping-pong configuration)

Table 59.  Interface: emif_usr_clk_secInterface type: Clock Output
Port Name Direction Description
emif_usr_clk_sec Output User clock domain. Intended for the secondary interface in a ping-pong configuration.