External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

5.1. Simulation Options

The following simulation options are available with the example testbench to improve simulation speed:
  • Full calibration—Calibrates the same way as in hardware, and includes all phase sweeps, delay adjustments, and data centering.
  • Skip calibration—Loads memory configuration settings and enters user mode, providing the fastest simulation time.
Note: For proper simulation of DQS Tracking, you must enable full calibration.

Both simulation options represent accurate controller efficiency and do not take into account board skew. This may cause a discrepancy in the simulated interface latency numbers. For more information regarding simulation assumptions and differences between RTL simulation and post-fit implementation, refer to the Simulation Versus Hardware Implementation chapter in the Arria® 10 EMIF IP Design Example User Guide.

Table 181.  Typical Simulation Times Using Arria® 10 EMIF IP

Calibration Mode/Run Time (1)

Estimated Simulation Time

Small Interface (×8 Single Rank)

Large Interface (×72 Quad Rank)


  • Full calibration
  • Includes all phase/delay sweeps and centering

20 minutes

~ 1 day


  • Skip calibration
  • Preloads calculated settings

10 minutes

25 minutes

Abstract PHY

  • Replace PHY and external memory model with a single abstract PHY model.
  • IMPORTANT: External memory model is NOT used in this mode. No I/O switching occurs to the external memory model.

1 minute

5 minutes

Note to Table:

  1. Uses one loop of driver test. One loop of driver is approximately 600 read or write requests, with burst length up to 64.
  2. Simulation times shown in this table are approximate measurements made using Synopsys VCS. Simulation times can vary considerably, depending on the IP configuration, the simulator used, and the computer or server used.