External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.1.7. PHY Clock Tree

Dedicated high-speed clock networks drive I/Os in Arria® 10 external memory interfaces. Each PHY clock network spans only one bank.

The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

All Arria® 10 external memory interfaces use the PHY clock trees.