External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

12.1.1. Timing Analysis

Timing analysis of Arria® 10 EMIF IP is somewhat simpler than that of earlier device families, because Arria® 10 devices have more hardened blocks and there are fewer soft logic registers to be analyzed, because most are user logic registers.

Your Arria® 10 EMIF IP includes a Synopsys Design Constraints File (.sdc) which contains timing constraints specific to your IP. The .sdc file also contains Tool Command Language (.tcl) scripts which perform various timing analyses specific to memory interfaces.

Two timing analysis flows are available for Arria® 10 EMIF IP:

  • Early I/O Timing Analysis, which is a precompilation flow.
  • Full Timing Analysis, which is a post-compilation flow.