External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 11/28/2024
Public
Document Table of Contents

4.1.3.10. afi_reset_n for LPDDR3

AFI reset interface

Table 86.  Interface: afi_reset_nInterface type: Reset Output
Port Name Direction Description
afi_reset_n Output Reset for the AFI clock domain. Asynchronous assertion and synchronous deassertion