External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

5.2.2. Abstract PHY Simulation

The Abstract PHY is a simulation model of the EMIF PHY that can decrease simulation time by 3-10 times. The Abstract PHY replaces the lane and the external memory model with a single model containing an internal memory array. No switching of the I/Os to the external memory model occurs when simulating with the Abstract PHY.

Abstract PHY reduces simulation time by two mechanisms:

  • The Nios processor has been disabled and is replaced by HDL forces that are applied at the beginning of simulation. The HDL forces are a minimum set of registers that configures the memory interface for simulation. The write and read latency values applied by the HDL forces are not representative of the post-calibration values applied to the memory interface running on hardware. However, as long as the customer logic is Avalon® and AFI-compliant, these values allow for successful RTL simulation.
  • The abstract PHY eliminates the need for full-speed clocks and therefore simulation of the Abstract PHY does not require full-speed clock simulation events.

To use the Abstract PHY, enable Simulation Options > Abstract PHY for fast simulation on the Diagnostic tab during EMIF IP generation. When you enable Abstract PHY, the EMIF IP is configured as shown below. The PHY RTL and external memory model are disconnected from the data path and in their place is the abstract PHY containing an internal memory array.

Figure 43. Abstract PHY
Note:
  • You cannot observe the external memory device signals when you are using Abstract PHY.
  • Abstract PHY does not reflect accurate latency numbers.
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