External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents Communication

Communication between the EMIF Toolkit and external memory interface connections is achieved using a JTAG Avalon® -MM master attached to the sequencer bus.

The following figure shows the structure of EMIF IP with JTAG Avalon® -MM master attached to sequencer bus masters.

Figure 121. EMIF IP with JTAG Avalon-MM Master

EMIF IP with JTAG Avalon-MM