External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 11/28/2024
Public
Document Table of Contents

4.1.2.27. ctrl_user_priority for DDR4

Controller user-requested priority interface

Table 69.  Interface: ctrl_user_priorityInterface type: Conduit
Port Name Direction Description
ctrl_user_priority_hi Input When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fullfilled before other low priority requests.