External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 11/28/2024
Public
Document Table of Contents

4.1.2.21. cal_debug_out_clk for DDR4

User calibration debug clock interface

Table 63.  Interface: cal_debug_out_clkInterface type: Clock Output
Port Name Direction Description
cal_debug_out_clk Output User clock domain