External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

5.2.4. Functional Simulation with Verilog HDL

Simulation scripts for the Synopsys* , Cadence, Aldec, and Siemens EDA simulators are provided for you to run the example design.

The simulation scripts are located in the following main folder locations:

Simulation scripts in the simulation folders are located as follows:

  • sim\ed_sim\mentor\msim_setup.tcl
  • sim\ed_sim\synopsys\vcs\vcs_setup.sh
  • sim\ed_sim\synopsys\vcsmx\vcsmx_setup.sh
  • sim\ed_sim\aldec\rivierapro_setup.tcl
  • sim\ed_sim\cadence\xcelium_setup.sh

For more information about simulating Verilog HDL or VHDL designs using command lines, refer to the Quartus® Prime Pro Edition User Guide, Third-party Simulation.