External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents OCT and ODT Usage

Modern external memory interface designs typically use OCT for the FPGA end of the line, and ODT for the memory component end of the line. If either the OCT or ODT are incorrectly configured or enabled, signal integrity problems occur.

If the design uses OCT, the RZQ pin must be placed correctly for the OCT to work. If you do not place the RZQ pin, the Quartus® Prime software allocates them automatically with the following warning:

Critical Warning (174073): No exact pin location assignment(s) 
for 1 RUP, RDN, or RZQ pins of 1 total RUP, RDN or RZQ pins.

Info (174074): RUP, RDN, or RZQ pin oct_rzqin not assigned to an exact 
location on the device

If you see these warnings, the RZQ pin may have been allocated to a pin that does not have the required external resistor present on the board. This allocation renders the OCT circuit faulty, resulting in unreliable calibration and or interface behavior. The pins with the required external resistor must be specified in the Quartus® Prime software.

For the FPGA, ensure that you perform the following:

  • Connect the RZQ pin to the correct resistors and pull-down to ground in the schematic or PCB.
  • Contain the RZQ pins within a bank of the device that is operating at the same VCCIO voltage as the interface that is terminated.
  • Review the Fitter Pin-Out file for RZQ pins to ensure that they are on the correct pins, and that only the correct number of calibration blocks exists in your design.
  • Check in the fitter report that the input, output, and bidirectional signals with calibrated OCT all have the termination control block applicable to the associated RZQ pins.

For the memory components, ensure that you perform the following:

  • Connect the required resistor to the correct pin on each and every component, and ensure that it is pulled to the correct voltage.
  • Place the required resistor close to the memory component.
  • Correctly configure the IP to enable the desired termination at initialization time.
  • Check that the speed grade of memory component supports the selected ODT setting.
  • Check that the second source part that may have been fitted to the PCB, supports the same ODT settings as the original