External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Public
Document Table of Contents

6.3.1.2. DIMM Options

Unbuffered DIMMs (UDIMMs) require one set of chip-select (CS#), on-die termination (ODT), clock-enable (CKE), and clock pair (CK/CKn) for every physical rank on the DIMM. Registered DIMMs use only one pair of clocks. DDR3 registered DIMMs require a minimum of two chip-select signals, while DDR4 requires only one.

Compared to the unbuffered DIMMs (UDIMM), registered and load-reduced DIMMs (RDIMMs and LRDIMMs, respectively) use at least two chip-select signals CS#[1:0] in DDR3 and DDR4 . Both RDIMMs and LRDIMMs require an additional parity signal for address, RAS#, CAS#, and WE# signals. A parity error signal is asserted by the module whenever a parity error is detected.

LRDIMMs expand on the operation of RDIMMs by buffering the DQ/DQS bus. Only one electrical load is presented to the controller regardless of the number of ranks, therefore only one clock enable (CKE) and ODT signal are required for LRDIMMs, regardless of the number of physical ranks. Because the number of physical ranks may exceed the number of physical chip-select signals, DDR3 LRDIMMs provide a feature known as rank multiplication, which aggregates two or four physical ranks into one larger logical rank. Refer to LRDIMM buffer documentation for details on rank multiplication.

The following table shows UDIMM and RDIMM pin options for DDR3.

Table 219.  UDIMM and RDIMM Pin Options for DDR3

Pins

UDIMM Pins (Single Rank)

UDIMM Pins

(Dual Rank)

RDIMM Pins (Single Rank)

RDIMM Pins

(Dual Rank)

Data

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0] =

{CB[7:0], DQ[63:0]}

72 bit DQ[71:0]=

{CB[7:0], DQ[63:0]}

Data Mask

DM[8:0]
DM[8:0]
DM[8:0]
DM[8:0]

Data Strobe

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

DQS[8:0] and DQS#[8:0]

Address

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

BA[2:0], A[15:0]

2 GB: A[13:0]

4 GB: A[14:0]

8 GB: A[15:0]

Clock

CK0/CK0#

CK0/CK0#, CK1/CK1#

CK0/CK0#

CK0/CK0#

Command

ODT, CS#, CKE, RAS#, CAS#, WE#

ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE#

ODT, CS#[1:0], CKE, RAS#, CAS#, WE# 2

ODT[1:0], CS#[1:0], CKE[1:0], RAS#, CAS#, WE#

Parity

PAR, ALERT

PAR, ALERT

Other Pins

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

SA[2:0], SDA, SCL, EVENT#, RESET#

The following table shows LRDIMM pin options for DDR3.

Table 220.  LRDIMM Pin Options for DDR3

Pins

LRDIMM Pins (x4, 2R)

LRDIMM (x4, 4R, RMF=1) 3

LRDIMM Pins (x4, 4R, RMF=2)

LRDIMM Pins (x4, 8R, RMF=2)

LRDIMM Pins (x4, 8R, RMF=4)

LRDIMM (x8, 4R, RMF=1) 3

LRDIMM Pins (x8, 4R, RMF=2)

Data

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

72 bit DQ [71:0]=

{CB [7:0], DQ [63:0]}

Data Mask

DM[8:0] DM[8:0]

Data Strobe

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[17:0] and DQS#[17:0]

DQS[8:0] and DQS#[8:0] DQS[8:0] and DQS#[8:0]

Address

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

  

BA[2:0], A[17:0]
-16GB:A[15:0]
32GB:A[16:0]
64GB:A[17:0]

  

BA[2:0], A[15:0]
-2GB:A[13:0]
4GB:A[14:0]
8GB:A[15:0]

BA[2:0], A[16:0]
-4GB:A[14:0]
8GB:A[15:0]
16GB:A[16:0]

Clock