External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 4/01/2024
Document Table of Contents

3.4. Periodic OCT Recalibration

Periodic OCT recalibration improves the accuracy of the on-chip termination values used by DDR4 Pseudo-open Drain (POD) I/Os. This feature periodically invokes the user-mode OCT calibration engine and updates the I/O buffer termination settings to compensate for variations in calibrated OCT settings caused by large changes in device operating temperature.

This feature is automatically enabled for DDR4 memory interfaces unless the IP does not meet the technical requirements, or if you explicitly disable the feature in the parameter editor.