External Memory Interfaces Arria® 10 FPGA IP User Guide

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ID 683106
Date 11/28/2024
Public
Document Table of Contents
Document Table of Contents x
1. Release Information 2. External Memory Interfaces Arria® 10 FPGA IP Introduction 3. Arria® 10 EMIF IP Product Architecture 4. Arria® 10 EMIF IP End-User Signals 5. Arria® 10 EMIF – Simulating Memory IP 6. Arria® 10 EMIF IP for DDR3 7. Arria® 10 EMIF IP for DDR4 8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme 9. Arria® 10 EMIF IP for QDR-IV 10. Arria® 10 EMIF IP for RLDRAM 3 11. Arria® 10 EMIF IP for LPDDR3 12. Arria® 10 EMIF IP Timing Closure 13. Optimizing Controller Performance 14. Arria® 10 EMIF IP Debugging 15. External Memory Interfaces Arria® 10 FPGA IP User Guide Archives 16. Document Revision History for External Memory Interfaces Arria® 10 FPGA IP User Guide
2. External Memory Interfaces Arria® 10 FPGA IP Introduction x
2.1. Arria® 10 EMIF IP Design Flow 2.2. Arria® 10 EMIF IP Design Checklist
3. Arria® 10 EMIF IP Product Architecture x
3.1. EMIF Architecture: Introduction 3.2. Arria® 10 EMIF Sequencer 3.3. Arria® 10 EMIF Calibration 3.4. Periodic OCT Recalibration 3.5. Arria® 10 EMIF Controller 3.6. Hardware Resource Sharing Among Multiple EMIFs 3.7. Arria® 10 EMIF for Hard Processor Subsystem 3.8. Arria® 10 EMIF Ping Pong PHY 3.9. Arria® 10 EMIF and SmartVID
3.1. EMIF Architecture: Introduction x
3.1.1. I/O Subsystem 3.1.2. I/O Column 3.1.3. I/O AUX 3.1.4. I/O Bank 3.1.5. I/O Lane 3.1.6. Input DQS Clock Tree 3.1.7. PHY Clock Tree 3.1.8. PLL Reference Clock Networks 3.1.9. Clock Phase Alignment
3.1.4. I/O Bank x
3.1.4.1. Implementing a x8 Interface with Hard Memory Controller 3.1.4.2. Implementing a x72 Interface with Hard Memory Controller
3.2. Arria® 10 EMIF Sequencer x
3.2.1. DQS Tracking
3.3. Arria® 10 EMIF Calibration x
3.3.1. Calibration Stages 3.3.2. Calibration Stages Descriptions 3.3.3. Calibration Algorithms 3.3.4. Calibration Flowchart
3.4. Periodic OCT Recalibration x
3.4.1. Operation 3.4.2. Technical Restrictions 3.4.3. Efficiency Impact
3.5. Arria® 10 EMIF Controller x
3.5.1. Hard Memory Controller 3.5.2. Hard Memory Controller Rate Conversion Feature
3.5.1. Hard Memory Controller x
3.5.1.1. Hard Memory Controller Features 3.5.1.2. Hard Memory Controller Main Control Path 3.5.1.3. Data Buffer Controller
3.6. Hardware Resource Sharing Among Multiple EMIFs x
3.6.1. I/O Aux Sharing 3.6.2. I/O Bank Sharing 3.6.3. PLL Reference Clock Sharing 3.6.4. Core Clock Network Sharing
3.7. Arria® 10 EMIF for Hard Processor Subsystem x
3.7.1. Restrictions on I/O Bank Usage for Arria® 10 EMIF IP with HPS 3.7.2. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces
3.8. Arria® 10 EMIF Ping Pong PHY x
3.8.1. Ping Pong PHY Feature Description 3.8.2. Ping Pong PHY Architecture 3.8.3. Ping Pong PHY Limitations 3.8.4. Ping Pong PHY Calibration 3.8.5. Using the Ping Pong PHY 3.8.6. Ping Pong PHY Simulation Example Design
4. Arria® 10 EMIF IP End-User Signals x
4.1. Interface and Signal Descriptions 4.2. AFI Signals 4.3. AFI 4.0 Timing Diagrams 4.4. Arria® 10 Memory Mapped Register (MMR) Tables
4.1. Interface and Signal Descriptions x
4.1.1. Intel Arria 10 EMIF IP Interfaces for DDR3 4.1.2. Intel Arria 10 EMIF IP Interfaces for DDR4 4.1.3. Intel Arria 10 EMIF IP Interfaces for LPDDR3 4.1.4. Intel Arria 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme 4.1.5. Intel Arria 10 EMIF IP Interfaces for QDR-IV 4.1.6. Intel Arria 10 EMIF IP Interfaces for RLDRAM 3
4.1.1. Intel Arria 10 EMIF IP Interfaces for DDR3 x
4.1.1.1. pll_ref_clk for DDR3 4.1.1.2. pll_locked for DDR3 4.1.1.3. pll_extra_clk_0 for DDR3 4.1.1.4. pll_extra_clk_1 for DDR3 4.1.1.5. pll_extra_clk_2 for DDR3 4.1.1.6. pll_extra_clk_3 for DDR3 4.1.1.7. oct for DDR3 4.1.1.8. mem for DDR3 4.1.1.9. status for DDR3 4.1.1.10. afi_reset_n for DDR3 4.1.1.11. afi_clk for DDR3 4.1.1.12. afi_half_clk for DDR3 4.1.1.13. afi for DDR3 4.1.1.14. emif_usr_reset_n for DDR3 4.1.1.15. emif_usr_clk for DDR3 4.1.1.16. emif_usr_reset_n_sec for DDR3 4.1.1.17. emif_usr_clk_sec for DDR3 4.1.1.18. cal_debug_reset_n for DDR3 4.1.1.19. cal_debug_clk for DDR3 4.1.1.20. cal_debug_out_reset_n for DDR3 4.1.1.21. cal_debug_out_clk for DDR3 4.1.1.22. clks_sharing_master_out for DDR3 4.1.1.23. clks_sharing_slave_in for DDR3 4.1.1.24. clks_sharing_slave_out for DDR3 4.1.1.25. ctrl_amm for DDR3 4.1.1.26. ctrl_auto_precharge for DDR3 4.1.1.27. ctrl_user_priority for DDR3 4.1.1.28. ctrl_ecc_user_interrupt for DDR3 4.1.1.29. ctrl_ecc_readdataerror for DDR3 4.1.1.30. ctrl_mmr_slave for DDR3 4.1.1.31. hps_emif for DDR3 4.1.1.32. cal_debug for DDR3 4.1.1.33. cal_debug_out for DDR3
4.1.2. Intel Arria 10 EMIF IP Interfaces for DDR4 x
4.1.2.1. pll_ref_clk for DDR4 4.1.2.2. pll_locked for DDR4 4.1.2.3. pll_extra_clk_0 for DDR4 4.1.2.4. pll_extra_clk_1 for DDR4 4.1.2.5. pll_extra_clk_2 for DDR4 4.1.2.6. pll_extra_clk_3 for DDR4 4.1.2.7. oct for DDR4 4.1.2.8. mem for DDR4 4.1.2.9. status for DDR4 4.1.2.10. afi_reset_n for DDR4 4.1.2.11. afi_clk for DDR4 4.1.2.12. afi_half_clk for DDR4 4.1.2.13. afi for DDR4 4.1.2.14. emif_usr_reset_n for DDR4 4.1.2.15. emif_usr_clk for DDR4 4.1.2.16. emif_usr_reset_n_sec for DDR4 4.1.2.17. emif_usr_clk_sec for DDR4 4.1.2.18. cal_debug_reset_n for DDR4 4.1.2.19. cal_debug_clk for DDR4 4.1.2.20. cal_debug_out_reset_n for DDR4 4.1.2.21. cal_debug_out_clk for DDR4 4.1.2.22. clks_sharing_master_out for DDR4 4.1.2.23. clks_sharing_slave_in for DDR4 4.1.2.24. clks_sharing_slave_out for DDR4 4.1.2.25. ctrl_amm for DDR4 4.1.2.26. ctrl_auto_precharge for DDR4 4.1.2.27. ctrl_user_priority for DDR4 4.1.2.28. ctrl_ecc_user_interrupt for DDR4 4.1.2.29. ctrl_ecc_readdataerror for DDR4 4.1.2.30. ctrl_mmr_slave for DDR4 4.1.2.31. hps_emif for DDR4 4.1.2.32. cal_debug for DDR4 4.1.2.33. cal_debug_out for DDR4
4.1.3. Intel Arria 10 EMIF IP Interfaces for LPDDR3 x
4.1.3.1. pll_ref_clk for LPDDR3 4.1.3.2. pll_locked for LPDDR3 4.1.3.3. pll_extra_clk_0 for LPDDR3 4.1.3.4. pll_extra_clk_1 for LPDDR3 4.1.3.5. pll_extra_clk_2 for LPDDR3 4.1.3.6. pll_extra_clk_3 for LPDDR3 4.1.3.7. oct for LPDDR3 4.1.3.8. mem for LPDDR3 4.1.3.9. status for LPDDR3 4.1.3.10. afi_reset_n for LPDDR3 4.1.3.11. afi_clk for LPDDR3 4.1.3.12. afi_half_clk for LPDDR3 4.1.3.13. afi for LPDDR3 4.1.3.14. emif_usr_reset_n for LPDDR3 4.1.3.15. emif_usr_clk for LPDDR3 4.1.3.16. cal_debug_reset_n for LPDDR3 4.1.3.17. cal_debug_clk for LPDDR3 4.1.3.18. cal_debug_out_reset_n for LPDDR3 4.1.3.19. cal_debug_out_clk for LPDDR3 4.1.3.20. clks_sharing_master_out for LPDDR3 4.1.3.21. clks_sharing_slave_in for LPDDR3 4.1.3.22. clks_sharing_slave_out for LPDDR3 4.1.3.23. ctrl_user_priority for LPDDR3 4.1.3.24. ctrl_mmr_slave for LPDDR3 4.1.3.25. cal_debug for LPDDR3 4.1.3.26. cal_debug_out for LPDDR3
4.1.4. Intel Arria 10 EMIF IP Interfaces for QDR II/II+/II+ Xtreme x
4.1.4.1. pll_ref_clk for QDR II/II+/II+ Xtreme 4.1.4.2. pll_locked for QDR II/II+/II+ Xtreme 4.1.4.3. pll_extra_clk_0 for QDR II/II+/II+ Xtreme 4.1.4.4. pll_extra_clk_1 for QDR II/II+/II+ Xtreme 4.1.4.5. pll_extra_clk_2 for QDR II/II+/II+ Xtreme 4.1.4.6. pll_extra_clk_3 for QDR II/II+/II+ Xtreme 4.1.4.7. oct for QDR II/II+/II+ Xtreme 4.1.4.8. mem for QDR II/II+/II+ Xtreme 4.1.4.9. status for QDR II/II+/II+ Xtreme 4.1.4.10. emif_usr_reset_n for QDR II/II+/II+ Xtreme 4.1.4.11. emif_usr_clk for QDR II/II+/II+ Xtreme 4.1.4.12. cal_debug_reset_n for QDR II/II+/II+ Xtreme 4.1.4.13. cal_debug_clk for QDR II/II+/II+ Xtreme 4.1.4.14. cal_debug_out_reset_n for QDR II/II+/II+ Xtreme 4.1.4.15. cal_debug_out_clk for QDR II/II+/II+ Xtreme 4.1.4.16. clks_sharing_master_out for QDR II/II+/II+ Xtreme 4.1.4.17. clks_sharing_slave_in for QDR II/II+/II+ Xtreme 4.1.4.18. clks_sharing_slave_out for QDR II/II+/II+ Xtreme 4.1.4.19. ctrl_amm for QDR II/II+/II+ Xtreme 4.1.4.20. cal_debug for QDR II/II+/II+ Xtreme 4.1.4.21. cal_debug_out for QDR II/II+/II+ Xtreme
4.1.5. Intel Arria 10 EMIF IP Interfaces for QDR-IV x
4.1.5.1. pll_ref_clk for QDR-IV 4.1.5.2. pll_locked for QDR-IV 4.1.5.3. pll_extra_clk_0 for QDR-IV 4.1.5.4. pll_extra_clk_1 for QDR-IV 4.1.5.5. pll_extra_clk_2 for QDR-IV 4.1.5.6. pll_extra_clk_3 for QDR-IV 4.1.5.7. oct for QDR-IV 4.1.5.8. mem for QDR-IV 4.1.5.9. status for QDR-IV 4.1.5.10. afi_reset_n for QDR-IV 4.1.5.11. afi_clk for QDR-IV 4.1.5.12. afi_half_clk for QDR-IV 4.1.5.13. afi for QDR-IV 4.1.5.14. emif_usr_reset_n for QDR-IV 4.1.5.15. emif_usr_clk for QDR-IV 4.1.5.16. cal_debug_reset_n for QDR-IV 4.1.5.17. cal_debug_clk for QDR-IV 4.1.5.18. cal_debug_out_reset_n for QDR-IV 4.1.5.19. cal_debug_out_clk for QDR-IV 4.1.5.20. clks_sharing_master_out for QDR-IV 4.1.5.21. clks_sharing_slave_in for QDR-IV 4.1.5.22. clks_sharing_slave_out for QDR-IV 4.1.5.23. ctrl_amm for QDR-IV 4.1.5.24. cal_debug for QDR-IV 4.1.5.25. cal_debug_out for QDR-IV
4.1.6. Intel Arria 10 EMIF IP Interfaces for RLDRAM 3 x
4.1.6.1. pll_ref_clk for RLDRAM 3 4.1.6.2. pll_locked for RLDRAM 3 4.1.6.3. pll_extra_clk_0 for RLDRAM 3 4.1.6.4. pll_extra_clk_1 for RLDRAM 3 4.1.6.5. pll_extra_clk_2 for RLDRAM 3 4.1.6.6. pll_extra_clk_3 for RLDRAM 3 4.1.6.7. oct for RLDRAM 3 4.1.6.8. mem for RLDRAM 3 4.1.6.9. status for RLDRAM 3 4.1.6.10. afi_reset_n for RLDRAM 3 4.1.6.11. afi_clk for RLDRAM 3 4.1.6.12. afi_half_clk for RLDRAM 3 4.1.6.13. afi for RLDRAM 3 4.1.6.14. cal_debug_reset_n for RLDRAM 3 4.1.6.15. cal_debug_clk for RLDRAM 3 4.1.6.16. cal_debug_out_reset_n for RLDRAM 3 4.1.6.17. cal_debug_out_clk for RLDRAM 3 4.1.6.18. clks_sharing_master_out for RLDRAM 3 4.1.6.19. clks_sharing_slave_in for RLDRAM 3 4.1.6.20. clks_sharing_slave_out for RLDRAM 3 4.1.6.21. cal_debug for RLDRAM 3 4.1.6.22. cal_debug_out for RLDRAM 3
4.2. AFI Signals x
4.2.1. AFI Clock and Reset Signals 4.2.2. AFI Address and Command Signals 4.2.3. AFI Write Data Signals 4.2.4. AFI Read Data Signals 4.2.5. AFI Calibration Status Signals 4.2.6. AFI Tracking Management Signals 4.2.7. AFI Shadow Register Management Signals
4.3. AFI 4.0 Timing Diagrams x
4.3.1. AFI Address and Command Timing Diagrams 4.3.2. AFI Write Sequence Timing Diagrams 4.3.3. AFI Read Sequence Timing Diagrams 4.3.4. AFI Calibration Status Timing Diagram
4.4. Arria® 10 Memory Mapped Register (MMR) Tables x
4.4.1. ctrlcfg0 4.4.2. ctrlcfg1 4.4.3. dramtiming0 4.4.4. sbcfg1 4.4.5. caltiming0 4.4.6. caltiming1 4.4.7. caltiming2 4.4.8. caltiming3 4.4.9. caltiming4 4.4.10. caltiming9 4.4.11. dramaddrw 4.4.12. sideband0 4.4.13. sideband1 4.4.14. sideband2 4.4.15. sideband3 4.4.16. sideband4 4.4.17. sideband5 4.4.18. sideband6 4.4.19. sideband7 4.4.20. sideband8 4.4.21. sideband9 4.4.22. sideband10 4.4.23. sideband11 4.4.24. sideband12 4.4.25. sideband13 4.4.26. dramsts 4.4.27. niosreserve0 4.4.28. niosreserve1 4.4.29. ecc3: ECC Error and Interrupt Configuration 4.4.30. ecc4: Status and Error Information 4.4.31. ecc5: Address of Most Recent SBE/DBE 4.4.32. ecc6: Address of Most Recent Correction Command Dropped
5. Arria® 10 EMIF – Simulating Memory IP x
5.1. Simulation Options 5.2. Simulation Walkthrough
5.2. Simulation Walkthrough x
5.2.1. Calibration Modes 5.2.2. Abstract PHY Simulation 5.2.3. Simulation Scripts 5.2.4. Functional Simulation with Verilog HDL 5.2.5. Functional Simulation with VHDL 5.2.6. Simulating the Design Example
6. Arria® 10 EMIF IP for DDR3 x
6.1. Parameter Descriptions 6.2. Board Skew Equations 6.3. Pin and Resource Planning 6.4. DDR3 Board Design Guidelines
6.1. Parameter Descriptions x
6.1.1. Intel Arria 10 EMIF IP DDR3 Parameters: General 6.1.2. Intel Arria 10 EMIF IP DDR3 Parameters: Memory 6.1.3. Intel Arria 10 EMIF IP DDR3 Parameters: Mem I/O 6.1.4. Intel Arria 10 EMIF IP DDR3 Parameters: FPGA I/O 6.1.5. Intel Arria 10 EMIF IP DDR3 Parameters: Mem Timing 6.1.6. Intel Arria 10 EMIF IP DDR3 Parameters: Board 6.1.7. Intel Arria 10 EMIF IP DDR3 Parameters: Controller 6.1.8. Intel Arria 10 EMIF IP DDR3 Parameters: Diagnostics 6.1.9. Intel Arria 10 EMIF IP DDR3 Parameters: Example Designs
6.2. Board Skew Equations x
6.2.1. Equations for DDR3 Board Skew Parameters
6.3. Pin and Resource Planning x
6.3.1. Interface Pins 6.3.2. FPGA Resources 6.3.3. Pin Guidelines for Arria® 10 EMIF IP
6.3.1. Interface Pins x
6.3.1.1. Estimating Pin Requirements 6.3.1.2. DIMM Options 6.3.1.3. Maximum Number of Interfaces
6.3.2. FPGA Resources x
6.3.2.1. OCT 6.3.2.2. PLL
6.3.3. Pin Guidelines for Arria® 10 EMIF IP x
6.3.3.1. General Guidelines 6.3.3.2. x4 DIMM Implementation 6.3.3.3. Command and Address Signals 6.3.3.4. Clock Signals 6.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 6.3.3.6. Resource Sharing Guidelines (Multiple Interfaces) 6.3.3.7. Ping-Pong PHY Implementation
6.4. DDR3 Board Design Guidelines x
6.4.1. Terminations and Slew Rates with Arria® 10 Devices 6.4.2. Channel Signal Integrity Measurement 6.4.3. Layout Approach 6.4.4. Design Layout Guidelines 6.4.5. Package Deskew
6.4.1. Terminations and Slew Rates with Arria® 10 Devices x
6.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 6.4.1.2. Choosing Terminations on Arria® 10 Devices 6.4.1.3. On-Chip Termination Recommendations for Arria® 10 Devices 6.4.1.4. Slew Rates
6.4.2. Channel Signal Integrity Measurement x
6.4.2.1. Importance of Accurate Channel Signal Integrity Information 6.4.2.2. Understanding Channel Signal Integrity Measurement 6.4.2.3. How to Enter Calculated Channel Signal Integrity Values 6.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
6.4.4. Design Layout Guidelines x
6.4.4.1. General Layout Guidelines 6.4.4.2. Layout Guidelines 6.4.4.3. Length Matching Rules 6.4.4.4. Spacing Guidelines 6.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 6.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
6.4.5. Package Deskew x
6.4.5.1. DQ/DQS/DM Deskew 6.4.5.2. Address and Command Deskew 6.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 6.4.5.4. Deskew Example 6.4.5.5. Package Migration
7. Arria® 10 EMIF IP for DDR4 x
7.1. Parameter Descriptions 7.2. Board Skew Equations 7.3. Pin and Resource Planning 7.4. DDR4 Board Design Guidelines
7.1. Parameter Descriptions x
7.1.1. Intel Arria 10 EMIF IP DDR4 Parameters: General 7.1.2. Intel Arria 10 EMIF IP DDR4 Parameters: Memory 7.1.3. Intel Arria 10 EMIF IP DDR4 Parameters: Mem I/O 7.1.4. Intel Arria 10 EMIF IP DDR4 Parameters: FPGA I/O 7.1.5. Intel Arria 10 EMIF IP DDR4 Parameters: Mem Timing 7.1.6. Intel Arria 10 EMIF IP DDR4 Parameters: Board 7.1.7. Intel Arria 10 EMIF IP DDR4 Parameters: Controller 7.1.8. Intel Arria 10 EMIF IP DDR4 Parameters: Diagnostics 7.1.9. Intel Arria 10 EMIF IP DDR4 Parameters: Example Designs
7.2. Board Skew Equations x
7.2.1. Equations for DDR4 Board Skew Parameters
7.3. Pin and Resource Planning x
7.3.1. Interface Pins 7.3.2. FPGA Resources 7.3.3. Pin Guidelines for Arria® 10 EMIF IP 7.3.4. Resource Sharing Guidelines (Multiple Interfaces)
7.3.1. Interface Pins x
7.3.1.1. Estimating Pin Requirements 7.3.1.2. DIMM Options 7.3.1.3. Maximum Number of Interfaces
7.3.2. FPGA Resources x
7.3.2.1. OCT 7.3.2.2. PLL
7.3.3. Pin Guidelines for Arria® 10 EMIF IP x
7.3.3.1. General Guidelines 7.3.3.2. x4 DIMM Implementation 7.3.3.3. Command and Address Signals 7.3.3.4. Clock Signals 7.3.3.5. Data, Data Strobes, DM/DBI, and Optional ECC Signals 7.3.3.6. alert_n Pin Termination Recommendation
7.4. DDR4 Board Design Guidelines x
7.4.1. Terminations and Slew Rates with Arria® 10 Devices 7.4.2. Channel Signal Integrity Measurement 7.4.3. Layout Approach 7.4.4. Design Layout Guidelines 7.4.5. Package Deskew
7.4.1. Terminations and Slew Rates with Arria® 10 Devices x
7.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 7.4.1.2. Dynamic On-Die Termination (ODT) in DDR4 7.4.1.3. Choosing Terminations on Arria® 10 Devices 7.4.1.4. On-Chip Termination Recommendations for Arria® 10 Devices 7.4.1.5. Slew Rates
7.4.2. Channel Signal Integrity Measurement x
7.4.2.1. Importance of Accurate Channel Signal Integrity Information 7.4.2.2. Understanding Channel Signal Integrity Measurement 7.4.2.3. How to Enter Calculated Channel Signal Integrity Values 7.4.2.4. Guidelines for Calculating DDR4 Channel Signal Integrity
7.4.4. Design Layout Guidelines x
7.4.4.1. General Layout Guidelines 7.4.4.2. Layout Guidelines 7.4.4.3. Length Matching Rules 7.4.4.4. Spacing Guidelines 7.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 7.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals 7.4.4.7. Additional Layout Guidelines for DDR4 Twin-die Devices
7.4.5. Package Deskew x
7.4.5.1. DQ/DQS/DM Deskew 7.4.5.2. Address and Command Deskew 7.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 7.4.5.4. Deskew Example 7.4.5.5. Package Migration
8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme x
8.1. Parameter Descriptions 8.2. Board Skew Equations 8.3. Pin and Resource Planning 8.4. QDR II/II+/II+ Xtreme Board Design Guidelines
8.1. Parameter Descriptions x
8.1.1. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: General 8.1.2. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Memory 8.1.3. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA I/O 8.1.4. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Timing 8.1.5. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Board 8.1.6. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Controller 8.1.7. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Diagnostics 8.1.8. Intel Arria 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Example Designs
8.2. Board Skew Equations x
8.2.1. Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Parameters
8.3. Pin and Resource Planning x
8.3.1. Interface Pins
8.3.1. Interface Pins x
8.3.1.1. Estimating Pin Requirements 8.3.1.2. Maximum Number of Interfaces 8.3.1.3. FPGA Resources 8.3.1.4. OCT 8.3.1.5. PLL 8.3.1.6. Pin Guidelines for Arria® 10 EMIF IP
8.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
8.3.1.6.1. General Guidelines 8.3.1.6.2. QDR II, QDR II+ and QDR II+ Xtreme SRAM Command Signals 8.3.1.6.3. QDR II, QDR II+ and QDR II+ Xtreme SRAM Address Signals 8.3.1.6.4. QDR II, QDR II+, and QDR II+ Xtreme SRAM Clock Signals 8.3.1.6.5. QDR II, QDR II+ and QDR II+ Xtreme SRAM Data, BWS, and QVLD Signals 8.3.1.6.6. Resource Sharing Guidelines (Multiple Interfaces)
8.4. QDR II/II+/II+ Xtreme Board Design Guidelines x
8.4.1. QDR II SRAM Configurations 8.4.2. General Layout Guidelines 8.4.3. QDR II Layout Guidelines 8.4.4. QDR II SRAM Layout Approach 8.4.5. Package Deskew 8.4.6. Package Migration 8.4.7. Slew Rates
9. Arria® 10 EMIF IP for QDR-IV x
9.1. Parameter Descriptions 9.2. Board Skew Equations 9.3. Pin and Resource Planning 9.4. QDR-IV Board Design Guidelines
9.1. Parameter Descriptions x
9.1.1. Intel Arria 10 EMIF IP QDR-IV Parameters: General 9.1.2. Intel Arria 10 EMIF IP QDR-IV Parameters: Memory 9.1.3. Intel Arria 10 EMIF IP QDR-IV Parameters: FPGA I/O 9.1.4. Intel Arria 10 EMIF IP QDR-IV Parameters: Mem Timing 9.1.5. Intel Arria 10 EMIF IP QDR-IV Parameters: Board 9.1.6. Intel Arria 10 EMIF IP QDR-IV Parameters: Controller 9.1.7. Intel Arria 10 EMIF IP QDR-IV Parameters: Diagnostics 9.1.8. Intel Arria 10 EMIF IP QDR-IV Parameters: Example Designs
9.2. Board Skew Equations x
9.2.1. Equations for QDR-IV Board Skew Parameters
9.3. Pin and Resource Planning x
9.3.1. Interface Pins
9.3.1. Interface Pins x
9.3.1.1. Estimating Pin Requirements 9.3.1.2. Maximum Number of Interfaces 9.3.1.3. FPGA Resources 9.3.1.4. OCT 9.3.1.5. PLL 9.3.1.6. Pin Guidelines for Arria® 10 EMIF IP 9.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
9.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
9.3.1.6.1. General Guidelines 9.3.1.6.2. QDR IV SRAM Commands and Addresses, AP, and AINV Signals 9.3.1.6.3. QDR IV SRAM Clock Signals 9.3.1.6.4. QDR IV SRAM Data, DINV, and QVLD Signals
9.4. QDR-IV Board Design Guidelines x
9.4.1. QDR-IV Layout Approach 9.4.2. General Layout Guidelines 9.4.3. QDR-IV Layout Guidelines 9.4.4. Package Deskew 9.4.5. Package Migration 9.4.6. Slew Rates
10. Arria® 10 EMIF IP for RLDRAM 3 x
10.1. Parameter Descriptions 10.2. Board Skew Equations 10.3. Pin and Resource Planning 10.4. RLDRAM 3 Board Design Guidelines
10.1. Parameter Descriptions x
10.1.1. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: General 10.1.2. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Memory 10.1.3. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: FPGA I/O 10.1.4. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Mem Timing 10.1.5. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Board 10.1.6. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Controller 10.1.7. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Diagnostics 10.1.8. Intel Arria 10 EMIF IP RLDRAM 3 Parameters: Example Designs
10.2. Board Skew Equations x
10.2.1. Equations for RLDRAM 3 Board Skew Parameters
10.3. Pin and Resource Planning x
10.3.1. Interface Pins
10.3.1. Interface Pins x
10.3.1.1. Estimating Pin Requirements 10.3.1.2. Maximum Number of Interfaces 10.3.1.3. FPGA Resources 10.3.1.4. OCT 10.3.1.5. PLL 10.3.1.6. Pin Guidelines for Arria® 10 EMIF IP 10.3.1.7. Resource Sharing Guidelines (Multiple Interfaces)
10.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
10.3.1.6.1. General Guidelines 10.3.1.6.2. RLDRAM 3 Commands and Addresses 10.3.1.6.3. RLDRAM 3 Clock Signals 10.3.1.6.4. RLDRAM 3 Data, DM and QVLD Signals
10.4. RLDRAM 3 Board Design Guidelines x
10.4.1. RLDRAM 3 Configurations 10.4.2. General Layout Guidelines 10.4.3. RLDRAM 3 Layout Guidelines 10.4.4. Layout Approach 10.4.5. Package Deskew 10.4.6. Package Migration
11. Arria® 10 EMIF IP for LPDDR3 x
11.1. Parameter Descriptions 11.2. Board Skew Equations 11.3. Pin and Resource Planning 11.4. LPDDR3 Board Design Guidelines
11.1. Parameter Descriptions x
11.1.1. Intel Arria 10 EMIF IP LPDDR3 Parameters: General 11.1.2. Intel Arria 10 EMIF IP LPDDR3 Parameters: Memory 11.1.3. Intel Arria 10 EMIF IP LPDDR3 Parameters: Mem I/O 11.1.4. Intel Arria 10 EMIF IP LPDDR3 Parameters: FPGA I/O 11.1.5. Intel Arria 10 EMIF IP LPDDR3 Parameters: Mem Timing 11.1.6. Intel Arria 10 EMIF IP LPDDR3 Parameters: Board 11.1.7. Intel Arria 10 EMIF IP LPDDR3 Parameters: Controller 11.1.8. Intel Arria 10 EMIF IP LPDDR3 Parameters: Diagnostics 11.1.9. Intel Arria 10 EMIF IP LPDDR3 Parameters: Example Designs
11.2. Board Skew Equations x
11.2.1. Equations for LPDDR3 Board Skew Parameters
11.3. Pin and Resource Planning x
11.3.1. Interface Pins
11.3.1. Interface Pins x
11.3.1.1. Estimating Pin Requirements 11.3.1.2. Maximum Number of Interfaces 11.3.1.3. FPGA Resources 11.3.1.4. OCT 11.3.1.5. PLL 11.3.1.6. Pin Guidelines for Arria® 10 EMIF IP
11.3.1.6. Pin Guidelines for Arria® 10 EMIF IP x
11.3.1.6.1. General Guidelines 11.3.1.6.2. LPDDR3 Clock Signal 11.3.1.6.3. LPDDR3 Command and Address Signal 11.3.1.6.4. LPDDR3 Data, Data Strobe, and DM Signals 11.3.1.6.5. Resource Sharing Guidelines (Multiple Interfaces)
11.4. LPDDR3 Board Design Guidelines x
11.4.1. Terminations and Slew Rates with Arria® 10 Devices 11.4.2. Channel Signal Integrity Measurement 11.4.3. Layout Approach 11.4.4. Design Layout Guidelines 11.4.5. Package Deskew
11.4.1. Terminations and Slew Rates with Arria® 10 Devices x
11.4.1.1. Dynamic On-Chip Termination (OCT) in Arria® 10 Devices 11.4.1.2. Choosing Terminations on Arria® 10 Devices 11.4.1.3. On-Chip Termination Recommendations for Arria® 10 Devices
11.4.2. Channel Signal Integrity Measurement x
11.4.2.1. Importance of Accurate Channel Signal Integrity Information 11.4.2.2. Understanding Channel Signal Integrity Measurement 11.4.2.3. How to Enter Calculated Channel Signal Integrity Values 11.4.2.4. Guidelines for Calculating DDR3 Channel Signal Integrity
11.4.4. Design Layout Guidelines x
11.4.4.1. General Layout Guidelines 11.4.4.2. Layout Guidelines 11.4.4.3. Length Matching Rules 11.4.4.4. Spacing Guidelines 11.4.4.5. Layout Guidelines for DDR3 and DDR4 SDRAM Wide Interface (>72 bits) 11.4.4.6. Fly-By Network Design for Clock, Command, and Address Signals
11.4.5. Package Deskew x
11.4.5.1. DQ/DQS/DM Deskew 11.4.5.2. Address and Command Deskew 11.4.5.3. Package Deskew Recommendations for Arria® 10 Devices 11.4.5.4. Deskew Example 11.4.5.5. Package Migration
12. Arria® 10 EMIF IP Timing Closure x
12.1. Timing Closure 12.2. Timing Report DDR 12.3. Optimizing Timing 12.4. Early I/O Timing Estimation
12.1. Timing Closure x
12.1.1. Timing Analysis
12.1.1. Timing Analysis x
12.1.1.1. PHY or Core 12.1.1.2. I/O Timing
12.1.1.2. I/O Timing x
12.1.1.2.1. Read Capture 12.1.1.2.2. Write 12.1.1.2.3. Address and Command 12.1.1.2.4. DQS Gating / Postamble 12.1.1.2.5. Write Leveling
12.4. Early I/O Timing Estimation x
12.4.1. Performing Early I/O Timing Analysis
13. Optimizing Controller Performance x
13.1. Interface Standard 13.2. Bank Management Efficiency 13.3. Data Transfer 13.4. Improving Controller Efficiency
13.4. Improving Controller Efficiency x
13.4.1. Auto-Precharge Commands 13.4.2. Latency 13.4.3. Calibration 13.4.4. Bank Interleaving 13.4.5. Additive Latency and Bank Interleaving 13.4.6. User-Controlled Refresh 13.4.7. Frequency of Operation 13.4.8. Series of Reads or Writes 13.4.9. Data Reordering 13.4.10. Starvation Control 13.4.11. Command Reordering 13.4.12. Bandwidth 13.4.13. Enable Command Priority Control
13.4.2. Latency x
13.4.2.1. Additive Latency
13.4.6. User-Controlled Refresh x
13.4.6.1. Back-to-Back User-Controlled Refresh Usage
14. Arria® 10 EMIF IP Debugging x
14.1. Interface Configuration Performance Issues 14.2. Functional Issue Evaluation 14.3. Timing Issue Characteristics 14.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer 14.5. Hardware Debugging Guidelines 14.6. Categorizing Hardware Issues 14.7. Debugging Arria® 10 EMIF IP 14.8. Using the Traffic Generator with the Generated Design Example
14.1. Interface Configuration Performance Issues x
14.1.1. Interface Configuration Bottleneck and Efficiency Issues
14.2. Functional Issue Evaluation x
14.2.1. Intel® IP Memory Model 14.2.2. Vendor Memory Model 14.2.3. Transcript Window Messages 14.2.4. Modifying the Example Driver to Replicate the Failure
14.3. Timing Issue Characteristics x
14.3.1. Evaluating FPGA Timing Issues 14.3.2. Evaluating External Memory Interface Timing Issues
14.4. Verifying Memory IP Using the Signal Tap II Logic Analyzer x
14.4.1. Signals to Monitor with the Signal Tap II Logic Analyzer
14.5. Hardware Debugging Guidelines x
14.5.1. Create a Simplified Design that Demonstrates the Same Issue 14.5.2. Measure Power Distribution Network 14.5.3. Measure Signal Integrity and Setup and Hold Margin 14.5.4. Vary Voltage 14.5.5. Operate at a Lower Speed 14.5.6. Determine Whether the Issue Exists in Previous Versions of Software 14.5.7. Determine Whether the Issue Exists in the Current Version of Software 14.5.8. Try A Different PCB 14.5.9. Try Other Configurations 14.5.10. Debugging Checklist
14.6. Categorizing Hardware Issues x
14.6.1. Signal Integrity Issues 14.6.2. Hardware and Calibration Issues
14.6.1. Signal Integrity Issues x
14.6.1.1. Characteristics of Signal Integrity Issues 14.6.1.2. Evaluating SignaI Integrity Issues
14.6.1.2. Evaluating SignaI Integrity Issues x
14.6.1.2.1. Skew 14.6.1.2.2. Crosstalk 14.6.1.2.3. Power System 14.6.1.2.4. Clock Signals 14.6.1.2.5. Read Data Valid Window and Eye Diagram 14.6.1.2.6. Write Data Valid Window and Eye Diagram 14.6.1.2.7. OCT and ODT Usage
14.6.2. Hardware and Calibration Issues x
14.6.2.1. Postamble Timing Issues and Margin 14.6.2.2. Intermittent Issue Evaluation
14.7. Debugging Arria® 10 EMIF IP x
14.7.1. Debugging With the External Memory Interface Debug Toolkit 14.7.2. On-Chip Debug Port for Arria® 10 EMIF IP 14.7.3. Efficiency Monitor and Protocol Checker
14.7.1. Debugging With the External Memory Interface Debug Toolkit x
14.7.1.1. User Interface 14.7.1.2. Communication 14.7.1.3. Setup and Use 14.7.1.4. Configuring Your EMIF IP for Use with the Debug Toolkit 14.7.1.5. Reports 14.7.1.6. On-Die Termination Calibration 14.7.1.7. Eye Diagram 14.7.1.8. Driver Margining for Arria® 10 EMIF IP 14.7.1.9. Example Tcl Script for Running the EMIF Debug Toolkit 14.7.1.10. Using the EMIF Debug Toolkit with Arria® 10 HPS Interfaces
14.7.1.4. Configuring Your EMIF IP for Use with the Debug Toolkit x
14.7.1.4.1. Daisy-Chaining Additional EMIF IP Cores for Debugging 14.7.1.4.2. General Workflow 14.7.1.4.3. Linking the Project to a Device 14.7.1.4.4. Establishing Communication to Connections 14.7.1.4.5. Selecting an Active Interface
14.7.1.8. Driver Margining for Arria® 10 EMIF IP x
14.7.1.8.1. Determining Margin
14.7.2. On-Chip Debug Port for Arria® 10 EMIF IP x
14.7.2.1. EMIF On-Chip Debug Port 14.7.2.2. Access Protocol
14.7.3. Efficiency Monitor and Protocol Checker x
14.7.3.1. Including the Efficiency Monitor and Protocol Checker in Your Generated IP 14.7.3.2. Running the Efficiency Monitor with the External Memory Debug Toolkit 14.7.3.3. Communicating Directly to the Efficiency Monitor and Protocol Checker
1. Release Information
2. External Memory Interfaces Arria® 10 FPGA IP Introduction
3. Arria® 10 EMIF IP Product Architecture
4. Arria® 10 EMIF IP End-User Signals
5. Arria® 10 EMIF – Simulating Memory IP
6. Arria® 10 EMIF IP for DDR3
7. Arria® 10 EMIF IP for DDR4
8. Arria® 10 EMIF IP for QDR II/II+/II+ Xtreme
9. Arria® 10 EMIF IP for QDR-IV
10. Arria® 10 EMIF IP for RLDRAM 3
11. Arria® 10 EMIF IP for LPDDR3
12. Arria® 10 EMIF IP Timing Closure
13. Optimizing Controller Performance
14. Arria® 10 EMIF IP Debugging
15. External Memory Interfaces Arria® 10 FPGA IP User Guide Archives
16. Document Revision History for External Memory Interfaces Arria® 10 FPGA IP User Guide

6.4.4.2. Layout Guidelines

The following table lists layout guidelines.

Unless otherwise specified, the guidelines in the following table apply to the following topologies:

  • DIMM—UDIMM topology
  • DIMM—RDIMM topology
  • DIMM—LRDIMM topology
  • Not all versions of the Quartus® Prime software support LRDIMM.
  • Discrete components laid out in UDIMM topology
  • Discrete components laid out in RDIMM topology

These guidelines are recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface.

For information on the simulation flow, refer to https://community.intel.com/t5/FPGA-Wiki/Arria-10-EMIF-Simulation-Guidance/ta-p/735201.

For supported frequencies and topologies, refer to the External Memory Interface Spec Estimator https://www.intel.com/content/www/us/en/programmable/support/support-resources/external-memory.html.

For frequencies greater than 800 MHz, when you are calculating the delay associated with a trace, you must take the FPGA package delays into consideration.

Table 223.  Layout Guidelines   (1)

Parameter

Guidelines

Decoupling Parameter

  • Make VTT voltage decoupling close to the components and pull-up resistors.
  • Connect decoupling caps between VTT and VDD using a 0.1F cap for every other VTT pin.
  • Use a 0.1 uF cap and 0.01 uF cap for every VDDQ pin.

Maximum Trace Length

  • Even though there are no hard requirements for minimum trace length, you need to simulate the trace to ensure the signal integrity. Shorter routes result in better timing.
  • For DIMM topology only:
    • Maximum trace length for all signals from FPGA to the first DIMM slot is 4.5 inches.
    • Maximum trace length for all signals from DIMM slot to DIMM slot is 0.425 inches.
  • For discrete components only:
    • Maximum trace length for address, command, control, and clock from FPGA to the first component must not be more than 7 inches.
    • Maximum trace length for DQ, DQS, DQS#, and DM from FPGA to the first component is 5 inches.

General Routing

  • Route over appropriate VCC and GND planes.
  • Keep signal routing layers close to GND and power planes.
Spacing Guidelines
  • Avoid routing two signal layers next to each other. Always make sure that the signals related to memory interface are routed between appropriate GND or power layers.
  • For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) for these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) these traces. (Where H is the vertical distance to the closest return path for that particular trace.)
  • For Clock traces: Maintain at least 5H spacing between two clock pair or a clock pair and any other memory interface trace. (Where H is the vertical distance to the closest return path for that particular trace.)

Clock Routing

  • Route clocks on inner layers with outer-layer run lengths held to under 500 mils (12.7 mm).
  • Route clock signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not exceed 0.69 tCK for DDR3. For different DIMM configurations, check the appropriate JEDEC* specification.
  • These signals should maintain the following spacings:
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Clocks should maintain a length-matching between positive (p) and negative (n) signals of ±2 ps, routed in parallel.
  • Space between different pairs should be at least two times the trace width of the differential pair to minimize loss and maximize interconnect density.
  • To avoid mismatched transmission line to via, Intel® recommends that you use Ground Signal Signal Ground (GSSG) topology for your clock pattern—GND|CLKP|CKLN|GND.
  • Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. Refer to the following figure.

Address and Command Routing

  • Route address and command signals in a daisy chain topology from the first SDRAM to the last SDRAM. The maximum length of the first SDRAM to the last SDRAM must not be more than 0.69 tCK for DDR3 and 1.5 tCK for DDR4 . For different DIMM configurations, check the appropriate JEDEC* specifications.
  • UDIMMs are more susceptible to cross-talk and are generally noisier than buffered DIMMs. Therefore, route address and command signals of UDIMMs on a different layer than data signals (DQ) and data mask signals (DM) and with greater spacing.
  • Do not route differential clock (CK) and clock enable (CKE) signals close to address signals.
  • Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. Refer to the following figure.

DQ, DM, and DQS Routing Rules

  • All the trace length matching requirements are from the FPGA package ball to the SDRAM package ball, which means you must consider trace mismatching on different DIMM raw cards.
  • Match in length all DQ, DQS, and DM signals within a given byte-lane group with a maximum deviation of ±10 ps.
  • Ensure to route all DQ, DQS, and DM signals within a given byte-lane group on the same layer to avoid layer to layer transmission velocity differences, which otherwise increase the skew within the group.
  • Do not count on FPGAs to deskew for more than 20 ps of DQ group skew. The skew algorithm only removes the following possible uncertainties:
    • Minimum and maximum die IOE skew or delay mismatch
    • Minimum and maximum device package skew or mismatch
    • Board delay mismatch of 20 ps
    • Memory component DQ skew mismatch
    • Increasing any of these four parameters runs the risk of the deskew algorithm limiting, failing to correct for the total observed system skew. If the algorithm cannot compensate without limiting the correction, timing analysis shows reduced margins.
  • For memory interfaces with leveling, the timing between the DQS and clock signals on each device calibrates dynamically to meet tDQSS. To make sure the skew is not too large for the leveling circuit’s capability, follow these rules:
    • Propagation delay of clock signal must not be shorter than propagation delay of DQS signal at every device: (CKi) – DQSi > 0; 0 < i < number of components – 1 . For DIMMs, ensure that the CK trace is longer than the longest DQS trace at the DIMM connector.
    • Total skew of CLK and DQS signal between groups is less than one clock cycle: (CKi+ DQSi) max – (CKi+ DQSi) min < 1 × tCK(If you are using a DIMM topology, your delay and skew must take into consideration values for the actual DIMM.)

Spacing Guidelines
  • Avoid routing two signal layers next to each other. Always ensure that the signals related to the memory interface are routed between appropriate GND or power layers.
  • For DQ/DQS/DM traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Address/Command/Control traces: Maintain at least 3H spacing between the edges (air-gap) of these traces, where H is the vertical distance to the closest return path for that particular trace.
  • For Clock traces: Maintain at least 5H spacing between two clock pairs or a clock pair and any other memory interface trace, where H is the vertical distance to the closest return path for that particular trace.

Quartus® Prime Software Settings for Board Layout

  • To perform timing analyses on board and I/O buffers, use a third-party simulation tool to simulate all timing information such as skew, ISI, crosstalk, and type the simulation result into the Board Settings tab in the parameter editor.
  • Do not use advanced I/O timing model (AIOT) or board trace model unless you do not have access to any third party tool. AIOT provides reasonable accuracy but tools like HyperLynx provide better results.

Notes to Table:

  1. For point-to-point and DIMM interface designs, refer to the Micron website, www.micron.com.
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