External Memory Interfaces Arria® 10 FPGA IP User Guide

ID 683106
Date 11/28/2024
Public
Document Table of Contents

4.1.5.15. emif_usr_clk for QDR-IV

User clock interface

Table 140.  Interface: emif_usr_clkInterface type: Clock Output
Port Name Direction Description
emif_usr_clk Output User clock domain